An Efficient Parallel Structure for ΣΔ Modulators for use in High Speed Switching Power Amplifiers

Switching amplifiers using Sigma-delta modulators have proven to be highly efficient but require high switching speeds. Implementing complete digital systems at the switching speed has prevented their use in higher speed applications. In this paper we propose a methodology for the parallelisation of sigma-delta modulators allowing for the partition of the switching amplifier into a low-speed and high speed sections. This will enable switching amplifiers to be used effectively at higher frequencies, and specifically for wireless applications

Arquiteturas paralelas avançadas para transmissores 5G totalmente digitais

The fifth generation of mobile communications (5G) is being prepared and should be rolled out in the early coming years. Massive number of Radio-Frequency (RF) front-ends, peak data rates of 10 Gbps (everywhere and everytime), latencies lower than 10 msec and huge device densities are some of the expected disruptive capabilities. At the same time, previous generations can not be jeopardized, fostering the design of novel flexible and highly integrated radio transceivers able to support the simultaneous transmission of multi-band and multi-standard signals. The concept of all-digital transmission is being pointed out as a promising architecture to cope with such challenging requirements, due to its fully digital radio datapath. This thesis is focused on the proposal and validation of fully integrated and advanced digital transmitter architectures that excel the state-of-the-art in different figures of merit, such as transmission bandwidth, spectral purity, carrier agility, flexibility, and multi-band capability. The first part of this thesis introduces the concept of all-digital RF transmission. In particular, the foundations inherent to this thematic line are given, together with the recent advances reported in the state-of-the-art architectures.The core of this thesis, containing the main developments achieved during the Ph.D. work, is then presented and discussed. The first key contribution to the state-of-the-art is the use of cascaded Delta-Sigma (∆Σ) architectures to relax the analog filtering requirements of the conventional All-Digital Transmitters while maintaining the constant envelope waveform. Then, it is presented the first reported architecture where Antenna Arrays are directly driven by single-chip and single-bit All-Digital Transmitters, with promising results in terms of simplification of the RF front-ends and overall flexibility. Subsequently, the thesis proposes the first reported RF-stage All-Digital Transmitter that can be embedded within a single Field-Programmable Gate Array (FPGA) device. Thereupon, novel techniques to enable the design of wideband All-Digital Transmitters are reported. Finally, the design of concurrent multi-band transmitters is introduced. In particular, the design of agile and flexible dual and triple bands All-DigitalTransmitter (ADT) is demonstrated, which is a very important topic for scenarios that demand carrier aggregation. This Ph.D. contributes withseveral advances to the state-of-the-art of RF all-digital transmitters.A quinta geração de comunicações móveis (5G) está a ser preparada e deve ser comercializada nos próximos anos. Algumas das caracterı́sticas inovadoras esperadas passam pelo uso de um número massivo de font-ends de Rádio-Frequência (RF), taxas de pico de transmissão de dados de 10 Gbps (em todos os lugares e em todas as ocasiões), latências inferiores a 10 mseg e elevadas densidades de dispositivos. Ao mesmo tempo, as gerações anteriores não podem ser ignoradas, fomentando o design de novos transceptores de rádio flexı́veis e altamente integrados, capazes de suportar a transmissão simultânea de sinais multi-banda e multi-standard. O conceito de transmissão totalmente digital é considerado como um tipo de arquitetura promissora para lidar com esses requisitos desafiantes, devido ao seu datapath de rádio totalmente digital. Esta tese é focada na proposta e validação de arquiteturas de transmissores digitais totalmente integradas e avançadas que ultrapassam o estado da arte em diferentes figuras de mérito, como largura de banda de transmissão, pureza espectral, agilidade de portadora, flexibilidade e capacidade multibanda. A primeira parte desta tese introduz o conceito de transmissores de RF totalmente digitais. Em particular, os fundamentos inerentes a esta linha temática são apresentados, juntamente com os avanços mais recentes do estado-da-arte. O núcleo desta tese, contendo os principais desenvolvimentos alcançados durante o trabalho de doutoramento, é então apresentado e discutido. A primeira contribuição fundamental para o estado da arte é o uso de arquiteturas em cascata com moduladores ∆Σ para relaxar os requisitos de filtragem analógica dos transmissores RF totalmente digitais convencionais, mantendo a forma de onda envolvente constante. Em seguida, é apresentada a primeira arquitetura em que agregados de antenas são excitados diretamente por transmissores digitais de um único bit inseridos num único chip, com resultados promissores em termos de simplificação dos front-ends de RF e flexibilidade em geral. Posteriormente, é proposto o primeiro transmissor totalmente digital RF-stage relatado que pode ser incorporado dentro de um único Agregado de Células Lógicas Programáveis. Novas técnicas para permitir o desenho de transmissores RF totalmente digitais de banda larga são também apresentadas. Finalmente, o desenho de transmissores simultâneos de múltiplas bandas é exposto. Em particular, é demonstrado o desenho de transmissores de duas e três bandas ágeis e flexı́veis, que é um tópico essencial para cenários que exigem agregação de múltiplas bandas.Apoio financeiro da Fundação para a Ciência e Tecnologia (FCT) no âmbito de uma bolsa de doutoramento, ref. PD/BD/105857/2014.Programa Doutoral em Telecomunicaçõe

Δ-Σ και MSLA Διαμορφωτές Σήματος

Σκοπός της παρούσας διπλωματικής, είναι αρχικά η κατανόηση των εννοιών που αφορούν την μετατροπή σήματος από τον ψηφιακό κόσμο στον αναλογικό, την υπερδειγματοληψία, την διαμόρφωση θορύβου και τα σφάλματα κβαντισμού. Στη συνέχεια γίνεται εισαγωγή και ανάλυση στους Δέλτα - Σίγμα διαμορφωτές σήματος πρώτου και δευτέρου βαθμού καθώς και σε συγκρίσεις μεταξύ τους. Έπειτα επεξηγείται ο αλγόριθμος MSLA και η εφαρμογή του στους Δ – Σ διαμορφωτές και τέλος παρατίθενται αποτελέσματα και ευρήματα του MSLA σε διάφορες εφαρμογές μέσω προσομοιώσεων.The purpose of this thesis is to primarily understand the basic concepts of signal conversion and processing from the digital to the analog world, oversampling, noise shaping and errors in quantization. Thereafter, a brief introduction and analysis on Sigma Delta modulators of first and second order as well as the comparison between them is being shown. Then the MSLA algorithm and its application in Delta Sigma modulators are explained and finally various applications through extensive simulations are presented

Radar systems for the water resources mission, volume 2

The application of synthetic aperture radar (SAR) in monitoring and managing earth resources was examined. The function of spaceborne radar is to provide maps and map imagery to be used for earth resource and oceanographic applications. Spaceborne radar has the capability of mapping the entire United States regardless of inclement weather; however, the imagery must have a high degree of resolution to be meaningful. Attaining this resolution is possible with the SAR system. Imagery of the required quality must first meet mission parameters in the following areas: antenna patterns, azimuth and range ambiguities, coverage, and angle of incidence

Design of a wideband low-power continuous-time sigma-delta (ΣΔ) analog-to-digital converter (ADC) in 90nm CMOS technology

The growing trend in VLSI systems is to shift more signal processing functionality from analog to digital domain to reduce manufacturing cost and improve reliability. It has resulted in the demand for wideband high-resolution analog-to-digital converters (ADCs). There are many different techniques for doing analog-to-digital conversions. Oversampling ADC based on sigma-delta (ΣΔ) modulation is receiving a lot of attention due to its significantly relaxed matching requirements on analog components. Moreover, it does not need a steep roll-off anti-aliasing filter. A ΣΔ ADC can be implemented either as a discrete time system or a continuous time one. Nowadays growing interest is focused on the continuous-time ΣΔ ADC for its use in the wideband and low-power applications, such as medical imaging, portable ultrasound systems, wireless receivers, and test equipments. A continuous-time ΣΔ ADC offers some important advantages over its discrete-time counterpart, including higher sampling frequency, intrinsic anti-alias filtering, much relaxed sampling network requirements, and low-voltage implementation. Especially it has the potential in achieving low power consumption. This dissertation presents a novel fifth-order continuous-time ΣΔ ADC which is implemented in a 90nm CMOS technology with single 1.0-V power supply. To speed up design process, an improved direct design method is proposed and used to design the loop filter transfer function. To maximize the in-band gain provided by the loop filter, thus maximizing in-band noise suppression, the excess loop delay must be kept minimum. In this design, a very low latency 4-bit flash quantizer with digital-to-analog (DAC) trimming is utilized. DAC trimming technique is used to correct the quantizer offset error, which allows minimum-sized transistors to be used for fast and low-power operation. The modulator has sampling clock of 800MHz. It achieves a dynamic range (DR) of 75dB and a signal-to-noise-and-distortion ratio (SNDR) of 70dB over 25MHz input signal bandwidth with 16.4mW power dissipation. Our work is among the most improved published to date. It uses the lowest supply voltage and has the highest input signal bandwidth while dissipating the lowest power among the bandwidths exceeding 15MHz

Space station tracking requirements feasibility study, volume 2

The objective of this feasibility study is to determine analytically the accuracies of various sensors being considered as candidates for Space Station use. Specifically, the studies were performed whether or not the candidate sensors are capable of providing the required accuracy, or if alternate sensor approaches should be investigated. Other topics related to operation in the Space Station environment were considered as directed by NASA-JSC. The following topics are addressed: (1) Space Station GPS; (2) Space Station Radar; (3) Docking Sensors; (4) Space Station Link Analysis; (5) Antenna Switching, Power Control, and AGC Functions for Multiple Access; (6) Multichannel Modems; (7) FTS/EVA Emergency Shutdown; (8) Space Station Information Systems Coding; (9) Wanderer Study; and (10) Optical Communications System Analysis. Brief overviews of the abovementioned topics are given. Wherever applicable, the appropriate appendices provide detailed technical analysis. The report is presented in two volumes. This is Volume 2, containing Appendices K through U