Low-Power, High-Speed Transceivers for Network-on-Chip Communication

Networks on chips (NoCs) are becoming popular as they provide a solution for the interconnection problems on large integrated circuits (ICs). But even in a NoC, link-power can become unacceptably high and data rates are limited when conventional data transceivers are used. In this paper, we present a low-power, high-speed source-synchronous link transceiver which enables a factor 3.3 reduction in link power together with an 80% increase in data-rate. A low-swing capacitive pre-emphasis transmitter in combination with a double-tail sense-amplifier enable speeds in excess of 9 Gb/s over a 2 mm twisted differential interconnect, while consuming only 130 fJ/transition without the need for an additional supply. Multiple transceivers can be connected back-to-back to create a source-synchronous transceiver-chain with a wave-pipelined clock, operating with 6sigma offset reliability at 5 Gb/s

High-resolution width-modulated pulse rebalance electronics for strapdown gyroscopes and accelerometers

Three different rebalance electronic loops were designed, implemented, and evaluated. The loops were width-modulated binary types using a 614.4 kHz keying signal; they were developed to accommodate the following three inertial sensors with the indicated resolution values: (1) Kearfott 2412 accelerometer - resolution = 260 micro-g/data pulse, (2) Honeywell GG334 gyroscope - resolution = 3.9 milli-arc-sec/data pulse, (3) Kearfott 2401-009 accelerometer - resolution = 144 milli-g/data pulse. Design theory, details of the design implementation, and experimental results for each loop are presented

Synchronous demodulator

A synchronous demodulator includes a switch which is operated in synchronism with an incoming periodic signal and both divides and applies that signal to two signal channels. The two channels each include a network for computing and holding, for a predetermined length of time, the average signal value on that channel and applies those valves, in the form of two other signals, to the inputs of a differential amplifier. The networks may be R-C networks. The output of the differential amplifier may or may not form the output of the synchronous detector and may or may not be filtered. The output will not include a periodic signal due to the presence of a dc offset. Additionally, the output will not contain any substantial ripple due to periodic components in the input signal. In a somewhat more complex version, containing twice the structural components of the above synchronous demodulator with a more complex switching mechanism, essentially all ripple due to periodic components in the input signal are eliminated

Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

Radiation and shielding study for the International Ultraviolet Explorer

Technical advisory services to ensure integrity of parts and material exposed to energetic particle radiation for the IUE scientific instruments, spacecraft, and subsystems are provided. A significant potential for interference, degradation, or failure for unprotected or sensitive items was found. Vulnerable items were identified, and appropriate tests, changes, and shields were defined

10 Gbit/s bit interleaving CDR for low-power PON

A novel, low power, downstream clock and data recovery (CDR)- decimator architecture is proposed for next generation, energy efficient 10 Gbit/s optical network units (ONUs). The architecture employs a new time division multiplexing bit-interleaving downstream concept for passive optical networks (Bi-PON) allowing early decimation of the incoming data and lowering of the processing speed to the user rate of the ONU, thus reducing the power consumption significantly

A neural probe with up to 966 electrodes and up to 384 configurable channels in 0.13 μm SOI CMOS

In vivo recording of neural action-potential and local-field-potential signals requires the use of high-resolution penetrating probes. Several international initiatives to better understand the brain are driving technology efforts towards maximizing the number of recording sites while minimizing the neural probe dimensions. We designed and fabricated (0.13-μm SOI Al CMOS) a 384-channel configurable neural probe for large-scale in vivo recording of neural signals. Up to 966 selectable active electrodes were integrated along an implantable shank (70 μm wide, 10 mm long, 20 μm thick), achieving a crosstalk of −64.4 dB. The probe base (5 × 9 mm2) implements dual-band recording and a 1