Design and implementation of a multi-modal sensor with on-chip security

With the advancement of technology, wearable devices for fitness tracking, patient monitoring, diagnosis, and disease prevention are finding ways to be woven into modern world reality. CMOS sensors are known to be compact, with low power consumption, making them an inseparable part of wireless medical applications and Internet of Things (IoT). Digital/semi-digital output, by the translation of transmitting data into the frequency domain, takes advantages of both the analog and digital world. However, one of the most critical measures of communication, security, is ignored and not considered for fabrication of an integrated chip. With the advancement of Moore\u27s law and the possibility of having a higher number of transistors and more complex circuits, the feasibility of having on-chip security measures is drawing more attention. One of the fundamental means of secure communication is real-time encryption. Encryption/ciphering occurs when we encode a signal or data, and prevents unauthorized parties from reading or understanding this information. Encryption is the process of transmitting sensitive data securely and with privacy. This measure of security is essential since in biomedical devices, the attacker/hacker can endanger users of IoT or wearable sensors (e.g. attacks at implanted biosensors can cause fatal harm to the user). This work develops 1) A low power and compact multi-modal sensor that can measure temperature and impedance with a quasi-digital output and 2) a low power on-chip signal cipher for real-time data transfer

Analog Realization of Arbitrary One-Dimensional Maps

An increasing number of applications of a one-dimensional (1-D) map as an information processing element are found in the literature on artificial neural networks, image processing systems, and secure communication systems. In search of an efficient hardware implementation of a 1-D map, we discovered that the bifurcating neuron (BN), which was introduced elsewhere as a mathematical model of a biological neuron under the influence of an external sinusoidal signal, could provide a compact solution. The original work on the BN indicated that its firing time sequence, when it was subject to a sinusoidal driving signal, was related to the sine-circle map, suggesting that the BN can compute the sine-circle map. Despite its rich array of dynamical properties, the mathematical description of the BN is simple enough to lend itself to a compact circuit implementation. In this paper, we generalize the original work and show that the computational power of the BN can be extended to compute an arbitrary 1-D map. Also, we describe two possible circuit models of the BN: the programmable unijunction transistor oscillator neuron, which was introduced in the original work as a circuit model of the BN, and the integrated-circuit relaxation oscillator neuron (IRON), which was developed for more precise modeling of the BN. To demonstrate the computational power of the BN, we use the IRON to generate the bifurcation diagrams of the sine-circle map, the logistic map, as well as the tent map, and then compare them with exact numerical versions. The programming of the BN to compute an arbitrary map can be done simply by changing the waveform of the driving signal, which is given to the BN externally; this feature makes the circuit models of the BN especially useful in the circuit implementation of a network of 1-D maps

On the Application of a Monolithic Array for Detecting Intensity-Correlated Photons Emitted by Different Source Types

It is not widely appreciated that many subtleties are involved in the accurate measurement of intensity-correlated photons; even for the original experiments of Hanbury Brown and Twiss (HBT). Using a monolithic 4x4 array of single-photon avalanche diodes (SPADs), together with an off-chip algorithm for processing streaming data, we investigate the difficulties of measuring second-order photon correlations g2 in a wide variety of light fields that exhibit dramatically different correlation statistics: a multimode He-Ne laser, an incoherent intensity-modulated lamp-light source and a thermal light source. Our off-chip algorithm treats multiple photon-arrivals at pixel-array pairs, in any observation interval, with photon fluxes limited by detector saturation, in such a way that a correctly normalized g2 function is guaranteed. The impact of detector background correlations between SPAD pixels and afterpulsing effects on second-order coherence measurements is discussed. These results demonstrate that our monolithic SPAD array enables access to effects that are otherwise impossible to measure with stand-alone detectors.Comment: 17 pages, 6 figure

Study of a Time-Domain Information Processing Integrated Circuit for a Large Scale Nonlinear Coupled System

本論文は，製造バラツキに頑健な大規模非線形結合系を実現するための，時間軸情報処理集積回路に関する論文である．実数値をとる非線形現象を呈する複雑系は，集積回路技術の進展により高性能化が進むデジタルコンピュータ上で解析されてきた．これにより非線形システムで観測される現象の理解が進み，蓄積された知見を情報処理に役立てようという機運が高まっている．これらの系は，もともと連続値を扱うアナログシステムであるため，デジタル/アナログ変換の不要なアナログ回路で実装するのが効率的である．アナログ回路で大規模非線形結合系を実装した例としては，高いエネルギー効率で画像処理を行う振動子アレイ集積回路や，カオス現象を利用して最適化問題を有限時間内に解くカオスニューロンシステム等があり，アナログ回路のエネルギー効率の高さと，非線形現象を利用することの重要性が示されている．しかしながら，大規模非線形結合系をアナログ集積回路として実装する際には，トランジスタの製造バラツキ等により非線形素子毎の特性がばらつくという問題がある．また，特性をハードウェア的に作りこむことで演算特性を実現するアナログ回路では，任意の非線形現象を再現することが困難である．任意の非線形変換を実現する方式としては，非線形電圧波形をパルス幅変調信号でキャパシタにサンプリングする電圧波形サンプリング方式が提案されている．そこで本研究では，製造バラツキ補償回路を搭載した電圧波形サンプリング方式による大規模非線形結合系集積回路を提案し，0.25 ミクロンCMOS LSI 技術で設計・試作した．試作した回路を測定・評価するとともに，試作チップを用いた実験系で様々な時空間パターンを生成できることを示した．また，同回路で各種セルオートマトンが実現できることを示した.九州工業大学博士学位論文 学位記番号:生工博甲第263号 学位授与年月日:平成28年3月25日第1章 序論|第2章 しきい値結合写像モデルとその拡張モデル|第3章 電圧サンプリング方式(VSM) と電流サンプリング方式(CSM) の原理とバラツキ耐性|第4章 製造バラツキに頑健なVSM 方式非線形変換集積回路の設計・試作・評価|第5章 拡張しきい値結合写像モデルを実現する集積回路の設計・試作・評価|第6章 考察|第7章 結論九州工業大学平成27年

Observation of bifurcations and hysteresis in experimentally coupled logistic maps

Acknowledgements C.G. acknowledges funds POS_NAC_2018_1_151237 from the Agencia Nacional de Investigación e Innovación (ANII), Uruguay. All authors acknowledge the Comisión Sectorial de Investigación Científica (CSIC), Uruguay (group grant ‘CSIC2018 – FID13 – grupo ID 722’).Peer reviewedPreprin

Reconstructing bifurcation diagrams only from time-series data generated by electronic circuits in discrete-time dynamical systems

Bifurcation-diagram reconstruction estimates various attractors of a system without observing all of them but only from observing several attractors with different parameter values. Therefore, the bifurcation-diagram reconstruction can be used to investigate how attractors change with the parameter values, especially for real-world engineering and physical systems for which only a limited number of attractors can be observed. Although bifurcation diagrams of various systems have been reconstructed from time-series data generated in numerical experiments, the systems that have been targeted for reconstructing bifurcation diagrams from time series measured from physical phenomena so far have only been continuous-time dynamical systems. In this paper, we reconstruct bifurcation diagrams only from time-series data generated by electronic circuits in discrete-time dynamical systems with different parameter values. The generated time-series datasets are perturbed by dynamical noise and contaminated by observational noise. To reconstruct the bifurcation diagrams only from the time-series datasets, we use an extreme learning machine as a time-series predictor because it has a good generalization property. Hereby, we expect that the bifurcation-diagram reconstruction with the extreme learning machine is robust against dynamical noise and observational noise. For quantitatively verifying the robustness, the Lyapunov exponents of the reconstructed bifurcation diagrams are compared with those of the bifurcation diagrams generated in numerical experiments and by the electronic circuits

18th IEEE Workshop on Nonlinear Dynamics of Electronic Systems: Proceedings

Proceedings of the 18th IEEE Workshop on Nonlinear Dynamics of Electronic Systems, which took place in Dresden, Germany, 26 – 28 May 2010.:Welcome Address ........................ Page I Table of Contents ........................ Page III Symposium Committees .............. Page IV Special Thanks ............................. Page V Conference program (incl. page numbers of papers) ................... Page VI Conference papers Invited talks ................................ Page 1 Regular Papers ........................... Page 14 Wednesday, May 26th, 2010 ......... Page 15 Thursday, May 27th, 2010 .......... Page 110 Friday, May 28th, 2010 ............... Page 210 Author index ............................... Page XII