A new monolithic approach for mid-IR focal plane arrays

Antimonide-based photodetectors have recently been grown on a GaAs substrate by molecular beam epitaxy (MBE) and reported to have comparable performance to the devices grown on more expensive InSb and GaSb substrates. We demonstrated that GaAs, in addition to providing a cost saving substrate for antimonide-based semiconductor growth, can be used as a functional material to fabricate transistors and realize addressing circuits for the heterogeneously grown photodetectors. Based on co-integration of a GaAs MESFET with an InSb photodiode, we recently reported the first demonstration of a switchable and mid-IR sensible photo-pixel on a GaAs substrate that is suitable for large-scale integration into a focal plane array. In this work we report on the fabrication steps that we had to develop to deliver the integrated photo-pixel. Various highly controllable etch processes, both wet and dry etch based, were established for distinct material layers. Moreover, in order to avoid thermally-induced damage to the InSb detectors, a low temperature annealed Ohmic contact was used, and the processing temperature never exceeded 180 °C. Furthermore, since there is a considerable etch step (> 6 μm) that metal must straddle in order to interconnect the fabricated devices, we developed an intermediate step using polyimide to provide a smoothing section between the lower MESFET and upper photodiode regions of the device. This heterogeneous technology creates great potential to realize a new type of monolithic focal plane array of addressable pixels for imaging in the medium wavelength infrared range without the need for flip-chip bonding to a CMOS readout chip

Silicon-on-insulator-based complementary metal oxide semiconductor integrated optoelectronic platform for biomedical applications

Microscale optical devices enabled by wireless power harvesting and telemetry facilitate manipulation and testing of localized biological environments (e.g., neural recording and stimulation, targeted delivery to cancer cells). Design of integrated microsystems utilizing optical power harvesting and telemetry will enable complex in vivo applications like actuating a single nerve, without the difficult requirement of extreme optical focusing or use of nanoparticles. Silicon-on-insulator (SOI)-based platforms provide a very powerful architecture for such miniaturized platforms as these can be used to fabricate both optoelectronic and microelectronic devices on the same substrate. Near-infrared biomedical optics can be effectively utilized for optical power harvesting to generate optimal results compared with other methods (e.g., RF and acoustic) at submillimeter size scales intended for such designs. We present design and integration techniques of optical power harvesting structures with complementary metal oxide semiconductor platforms using SOI technologies along with monolithically integrated electronics. Such platforms can become the basis of optoelectronic biomedical systems including implants and lab-on-chip systems

Ultra-Low Power Circuit Design for Miniaturized IoT Platform

This thesis examines the ultra-low power circuit techniques for mm-scale Internet of Things (IoT) platforms. The IoT devices are known for their small form factors and limited battery capacity and lifespan. So, ultra-low power consumption of always-on blocks is required for the IoT devices that adopt aggressive duty-cycling for high power efficiency and long lifespan. Several problems need to be addressed regarding IoT device designs, such as ultra-low power circuit design techniques for sleep mode and energy-efficient and fast data rate transmission for active mode communication. Therefore, this thesis highlights the ultra-low power always-on systems, focusing on energy efficient optical transmission in order to miniaturize the IoT systems. First, this thesis presents a battery-less sub-nW micro-controller for an always-operating system implemented with a newly proposed logic family. Second, it proposes an always-operating sub-nW light-to-digital converter to measure instant light intensity and cumulative light exposure, which employs the characteristics of this proposed logic family. Third, it presents an ultra-low standby power optical wake-up receiver with ambient light canceling using dual-mode operation. Finally, an energy-efficient low power optical transmitter for an implantable IoT device is suggested. Implications for future research are also provided.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/145862/1/imhotep_1.pd

Optimized Integrated PIN Photodiodes with Improved Backend Layers

This paper constitutes a systematic analysis of the impact of low- doped intrinsic base material, different bottom anti-reflective coatings and dielectric filter deposition on the electrical and optical performance of Si photodiodes processed in standard CMOS fabrication processes. Photodiode designs cover full area as well as interdigitated variants. Optimization of the photodiode’s spectral responsivity for a specific wavelength has been achieved by different bottom anti-reflective coating concepts as well as direct deposition of interference filters on Si-wafer. While standard bottom anti-reflective coating is the most efficient way of optimizing the optical response, embedded bottom anti-reflective coating offers the possibility of additional interference filter deposition directly on the wafer. For full area photodiodes with respective anti-reflective coating in place, the photodiode’s quantum efficiency approaches 100 % for l=750 nm. For interdigitated photodiodes, the spectral responsivity in the wavelength range of 400 nm to 500 nm can be significantly enhanced compared to full area photodiodes and show values as high as 0.21 A/W @ 400 nm and 0.37 A/W @ 500 nm. Optimized blue photodiodes are not sensible to iEPI thicknesses and have a leakage current of 10 pA for a 150 µm ´ 150 µm square photodiode

A Silicon p-i-n detector for a hybrid CMOS imaging system

A fully depleted silicon p-i-n image sensor for a very low noise hybrid CMOS imaging system was simulated, fabricated, and electrically characterized. The image sensor was then bonded to the foundry fabricated CMOS circuitry to create the imaging system. SILVACO Atlas was used to simulate the steady state electrical operation of the device as well as the optical response. Revisions were made to an existing mask set to allow the use of both contact and projection lithography in the fabrication process. Significant process improvements were introduced to eliminate needless complexity and reduce leakage current from the previously reported 1.5x10-6 A/cm2 below the goal of 2.2x10-9 A/cm2. Following fabrication of the image sensors, electrical testing was performed to verify diode quality from leakage and lifetime measurements. A lift-off process was developed for thick metal layers used in the bump-bond hybridization process. Daisy-chain test parts were created to characterize the mechanical and electrical connections formed in the hybridization process. Fabricated p-i-n photodiode arrays were diced and hybridized to read-out integrated circuits using a flip-chip bump bond process with indium interconnects. Testing of hybridized devices is currently ongoing

PNP PIN bipolar phototransistors for high-speed applications built in a 180nm CMOS process

AbstractThis work reports on three speed optimized pnp bipolar phototransistors build in a standard 180nm CMOS process using a special starting wafer. The starting wafer consists of a low doped p epitaxial layer on top of the p substrate. This low doped p epitaxial layer leads to a thick space-charge region between base and collector and thus to a high −3dB bandwidth at low collector–emitter voltages. For a further increase of the bandwidth the presented phototransistors were designed with small emitter areas resulting in a small base-emitter capacitance. The three presented phototransistors were implemented in sizes of 40×40μm2 and 100×100μm2. Optical DC and AC measurements at 410nm, 675nm and 850nm were done for phototransistor characterization. Due to the speed optimized design and the layer structure of the phototransistors, bandwidths up to 76.9MHz and dynamic responsivities up to 2.89A/W were achieved. Furthermore simulations of the electric field strength and space-charge regions were done

Low-power and high-detectivity Ge photodiodes by in-situ heavy As doping during Ge-on-Si seed layer growth

Germanium (Ge)-based photodetectors have become one of the mainstream components in photonic-integrated circuits (PICs). Many emerging PIC applications require the photodetectors to have high detectivity and low power consumption. Herein, we demonstrate high-detectivity Ge vertical p-i-n photodiodes on an in-situ heavily arsenic (As)-doped Ge-on-Si platform. The As doping was incorporated during the initial Ge-on-Si seed layer growth. The grown film exhibits an insignificant up-diffusion of the As dopants. The design results in a ∼45× reduction on the dark current and consequently a ∼5× enhancement on the specific detectivity (D*) at low reverse bias. The improvements are mainly attributed to the improved epi-Ge crystal quality and the narrowing of the device junction depletion width. Furthermore, a significant deviation on the AsH3 flow finds a negligible effect on the D* enhancement. This unconventional but low-cost approach provides an alternative solution for future high-detectivity and low-power photodiodes in PICs. This method can be extended to the use of other n-type dopants (e.g., phosphorus (P) and antimony (Sb)) as well as to the design of other types of photodiodes (e.g., waveguide-integrated)