Analysis and Characterization of a SiGe BiCMOS Low Power Operational Amplifier

Integrated circuit design for space applications can require radiation immunity, cryogenic operation and low power consumption. This thesis provides analysis and characterization of a SiGe BiCMOS low power operational amplifier (op amp) designed for lunar surface applications. The op amp has been fabricated on a commercially available 0.35-micron Silicon-Germanium (SiGe) BiCMOS process. The Heterojunction bipolar transistors (HBT) available in the SiGe process have been used in this op amp to take advantage of the total ionizing dose (TID) irradiation immunity and superb cryogenic operation, along with PMOS devices that show better TID immunity than their NMOS counterparts. The key features of the op amp include rail-to-rail output voltage swing, low input offset voltage, high open-loop gain and low supply current. The characterization of op amp is done for extreme temperatures and the results demonstrate that the op amp is fully functional across the lunar surface temperature range of −180°C to +120°C. The wide temperature operation of this op amp is tested using different bias current techniques such as proportional-to-absolute-temperature current, constant current and constant inversion coefficient current sources to investigate optimal biasing strategies for BiCMOS analog design. In addition, the SiGe BiCMOS low power op amp provides lower power consumption with the same or better unity-gain bandwidth when compared to a CMOS op amp with similar circuit topology

Developing a framework of non-fatal occupational injury surveillance for risk control in palm oil mills

Non-fatal occupational injury (NFOI) and its risk factors have become a current global concern. The need of research towards the relationship between occupational injury and its risk factor is essential, to fulfil the purpose and setting the priority of implementing safety preventive approaches at workplace. This research intended to develop a framework of NFOI surveillance by using epidemiological data, noise exposure data and NFOI data among palm oil mills’ workers. A total of 420 respondents who assigned in operation and processing areas (OP) (n=333) and general or office workers (n=87) had voluntary participated in this research. A questionnaire session with respondents was held to obtain epidemiological data and NFOI information via validated questionnaire. Noise hazard monitoring was executed by using Sound Level Meter (SLM) for environmental noise monitoring and Personal Sound Dosimeter for personal noise monitoring. Gathered data were analysed in quantitative method by using statistical software IBM SPSS Statistic version 21 and a risk matrix table for injury risk rating evaluation. It was discovered that high noise exposure level (≥ 85 dB[A]) was significantly associated with non-fatal occupational injury among OP workers (φ=0.123, p<0.05) with OR=1.87 (95% CI, 1.080-3.235, p<0.05). Risk rating for reported NFOI was at moderate level, with minor cuts and scratches were the dominant type of injury (42.6%). Analysis of logistic regression indicated that working in shift, not wearing protective gloves, health problems such as shortness of breath and ringing in ears, and excessive noise level (≥ 85 dB[A]) were the risk factors of NFOI in palm oil mills among OP workers. A framework of nonfatal injury surveillance in palm oil mills was developed based on the findings with integration of risk management process and injury prevention principles. This framework is anticipated to help the management in decision making for preventive actions and early detection of occupational health effects among workers

A low-offset low-voltage CMOS Op Amp with rail-to-rail input and output ranges

A low voltage CMOS op amp is presented. The circuit uses complementary input pairs to achieve a rail-to-rail common mode input voltage range. Special attention has been given to the reduction of the op amp's systematic offset voltage. Gain boost amplifiers are connected in a special way to provide not only an increase of the low-frequency open-loop gain but also a significant reduction of the systematic offset voltag

Physical design of low power operational amplifier

A CMOS single output two stage operational amplifier is presented which operates at 3 V power supply at 0.18 micron (i.e., 180 nm) technology. It is designed to meet a set of provided specifications. The unique behavior of the MOS transistors in sub- threshold region not only allows a designer to work at low input bias current but also at low voltage. This op-amp has very low standby power consumption with a high driving capability and operates at low voltage so that the circuit operates at low power. The op-amp provides a gain of 20.4dB and a -3db bandwidth of 202 kHz and a unity gain bandwidth of 2.15MHz for a load of 5 pF capacitor. This op-amp has a PSRR (+) of 85.0 dB and a PSRR (-) of 60.0 dB. It has a CMRR (dc) of -64.4 dB, and an output slew rate of 12.465 v/µs. The power consumption for the op-amp is 1.18mW. The presented op-amp has a Input Common Mode Range(ICMR) of -1V to 2.4V. The op-amp is designed in the 180 nm technology using the umc 180 nm technology library. The layout for the above op-amp had been designed and the post layout simulations are compared with the schematic simulations. The proposed op-amp is a simple two stage single ended op-amp. The input stage of the op-amp is a differential amplifier with an NMOS pair. The second stage of the op-amp is a simple PMOS common source amplifier. The second stage is used to increase the voltage swing at the output. The op-amp uses a -3v Vdd and a -3v Vss and consumes a power of around 0.6mW (as per post layout simulations)

A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

© 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio

A 0.18µm CMOS DDCCII for Portable LV-LP Filters

In this paper a current mode very low voltage (LV) (1V) and low power (LP) (21 µW) differential difference second generation current conveyor (CCII) is presented. The circuit is developed by applying the current sensing technique to a fully balanced version of a differential difference amplifier (DDA) so to design a suitable LV LP integrated version of the so-called differential difference CCII (DDCCII). Post-layout results, using a 0.18µm SMIC CMOS technology, have shown good general circuit performances making the proposed circuit suitable for fully integration in battery portable systems as, for examples, fully differential Sallen-Key bandpass filter

Single-amplifier integrator-based low power CMOS filter for video frequency applications

“This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”This paper describes a new low power fully differential second-order continuous-time low pass filter for use at video frequencies. The filter uses a single active device in combination with MOSFET resistors and grounded capacitors to achieve very low power consumption, small chip area and large dynamic range. The ideal integrator is realised using an internally compensated opamp consisting of only current mirrors and voltage buffers, whilst the lossy integrator is implemented by a single passive RC circuit. The filter has been simulated using a CMOS process. Results show that with a single 5 V power supply, cut-off frequency can be tuned from 3.5 MHz to 8 MHz, dynamic range is better than 67 dB, and power consumption is less than 1.7 mW