111 research outputs found
Integrated Electronics for Wireless Imaging Microsystems with CMUT Arrays
Integration of transducer arrays with interface electronics in the form of single-chip CMUT-on-CMOS has emerged into the field of medical ultrasound imaging
and is transforming this field. It has already been used in several commercial products such as handheld full-body imagers and it is being implemented by commercial and academic groups for Intravascular Ultrasound and Intracardiac Echocardiography. However, large attenuation of ultrasonic waves transmitted through
the skull has prevented ultrasound imaging of the brain. This research is a prime
step toward implantable wireless microsystems that use ultrasound to image the
brain by bypassing the skull. These microsystems offer autonomous scanning
(beam steering and focusing) of the brain and transferring data out of the brain for
further processing and image reconstruction.
The objective of the presented research is to develop building blocks of an integrated electronics architecture for CMUT based wireless ultrasound imaging systems while providing a fundamental study on interfacing CMUT arrays with their
associated integrated electronics in terms of electrical power transfer and acoustic
reflection which would potentially lead to more efficient and high-performance
systems.
A fully wireless architecture for ultrasound imaging is demonstrated for the
first time. An on-chip programmable transmit (TX) beamformer enables phased
array focusing and steering of ultrasound waves in the transmit mode while its
on-chip bandpass noise shaping digitizer followed by an ultra-wideband (UWB)
uplink transmitter minimizes the effect of path loss on the transmitted image data
out of the brain. A single-chip application-specific integrated circuit (ASIC) is de-
signed to realize the wireless architecture and interface with array elements, each
of which includes a transceiver (TRX) front-end with a high-voltage (HV) pulser,
a high-voltage T/R switch, and a low-noise amplifier (LNA). Novel design techniques are implemented in the system to enhance the performance of its building
blocks.
Apart from imaging capability, the implantable wireless microsystems can include a pressure sensing readout to measure intracranial pressure. To do so, a
power-efficient readout for pressure sensing is presented. It uses pseudo-pseudo
differential readout topology to cut down the static power consumption of the sensor for further power savings in wireless microsystems.
In addition, the effect of matching and electrical termination on CMUT array
elements is explored leading to new interface structures to improve bandwidth
and sensitivity of CMUT arrays in different operation regions. Comprehensive
analysis, modeling, and simulation methodologies are presented for further investigation.Ph.D
๋ฉ๋ชจ๋ฆฌ ์ธํฐํ์ด์ค๋ฅผ ์ํ 4 ๋ ๋ฒจ ํ์ค ์งํญ ๋ณ์กฐ ์ฟผํฐ ๋ ์ดํธ ์์ ๊ธฐ ์ค๊ณ
ํ์๋
ผ๋ฌธ(๋ฐ์ฌ) -- ์์ธ๋ํ๊ต๋ํ์ : ๊ณต๊ณผ๋ํ ์ ๊ธฐยท์ ๋ณด๊ณตํ๋ถ, 2022. 8. ๊น์ํ.๋ณธ ์ฐ๊ตฌ์์๋ ๋ฉ๋ชจ๋ฆฌ ์ธํฐํ์ด์ค๋ฅผ ์ํ 4 ๋ ๋ฒจ ํ์ค ์งํญ ๋ณ์กฐ (PAM-4) ์์ ๊ธฐ์ ์ง๊ต ํด๋ก์ ์์ฑํ๋ ์ง๊ต ์ ํธ ๋ณด์ ๊ธฐ๋ฅผ ์ ์๋๋ค. ๋ฐ์ดํฐ ์ผํฐ์์ ์ฆ๊ฐํ๋ IP ํธ๋ํฝ์ ๊ณ ์ ๋ฐ ์ ์ ๋ ฅ ๋ฉ๋ชจ๋ฆฌ ์ธํฐํ์ด์ค์ ๋ํ ์์๋ฅผ ์ฆ๊ฐ์์ผ์๋ค. ์ด๋ฌํ ์๊ตฌ๋ฅผ ๋ง์กฑ์ํค๊ธฐ ์ํด ํด๋ญ ๋ฐ ๋์ดํด์คํธ ์ฃผํ์๋ฅผ ๋์ด์ง ์๊ณ ๋ ๋ฐ์ดํฐ ์ ์ก๋ฅ ์ ๋์ผ ์ ์๋ PAM-4 ์ ํธ๊ฐ ์ฃผ๋ชฉ์ ๋ฐ๊ณ ์๋ค.
PAM-4 ์ ํธ๋ ์ ๋ก ๋น ๋ณต๊ท ์ ํธ (NRZ) ๋ณด๋ค 3๋ฐฐ ๋ฎ์ ์์ง ๋ง์ง์ ๊ฐ์ง๋ฉฐ, ์ด๋ ๊ฒฐ์ ํผ๋๋ฐฑ ์ดํ๋ผ์ด์ ๋ด ์ฌ๋ผ์ด์ค์ ํด๋ญ-ํ ๋๋ ์ด๋ฅผ ์ฆ๊ฐ์ํค๋ฉฐ, ์ด๋ก ์ธํด PAM-4 ๊ฒฐ์ ํผ๋๋ฐฑ ์ดํ๋ผ์ด์ ์ ์ฑ๋ฅ์ ์ ํํ๋ ์์ธ์ด๋ค.
๋ณธ ์ฐ๊ตฌ์์๋ ์ธ๋ฒํฐ ๊ธฐ๋ฐ์ ํฉ์ฐ๊ธฐ๋ฅผ ์ด์ฉ, ์ ํ์ ์ผ๋ก ์ ํธ๋ฅผ ์ฆํญ์ํค๋ ๊ฒฐ์ ํผ๋๋ฐฑ ์ดํ๋ผ์ด์ ๋ฅผ ์ฌ์ฉํจ์ผ๋ก์จ ์ฌ๋ผ์ด์์ ์ ๋ ฅ ์๋ชจ๋ฅผ ์ฆ๊ฐ์ํค์ง ์์ผ๋ฉด์ ์ฌ๋ผ์ด์์ ํด๋ญ-ํ ๋๋ ์ด๋ฅผ ์ค์ผ ์ ์๋ค.
๋ํ, ์ ์ํ ์ง์ฐ ์ด๋ ์ปจํธ๋กค๋ฌ๋ฅผ ํฌํจํ๋ ์ง๊ต ์ ํธ ๋ณด์ ๊ธฐ๋ ๋์ ์ ํ๋์ ๋น ๋ฅธ ์คํ ๋ณด์ ์ผ๋ก ์ฟผ๋๋ฌ์ฒ ํด๋ญ ๊ฐ์ ์คํ๋ฅผ ๊ต์ ํ ์ ์๋ค.
์ ํ์ ๋ ์ฆํญ ๊ฒฐ์ ํผ๋๋ฐฑ ์ดํ๋ผ์ด์ ์ ์ ์ํ ์ง์ฐ ์ด๋ ์ปจํธ๋กค๋ฌ๋ฅผ ํฌํจํ๋ ์ง๊ต ์ ํธ ๋ณด์ ๊ธฐ์ ์ฑ๋ฅ์ ๊ฒ์ฆํ๊ธฐ ์ํด ํ๋กํ ํ์
์นฉ์ ์ ์ํ์๋ค. ์ ์๋ ์นฉ์ 65 nm CMOS ๊ณต์ ์ผ๋ก ์ ์๋์๋ค. ํ๋กํ ํ์
์นฉ์ 24 Gb/s/pin ์์ 10-12 ์ ๋นํธ ์๋ฌ์จ์ 100 mUI ์ ์ ํธ ๋๋น๋ก ๋ฌ์ฑํ์๋ค. ํ๋กํ ํ์
์นฉ ๋ด PAM-4 ์์ ๊ธฐ๋ 0.73 pJ/b ์ ์๋์ง ํจ์จ์ ๊ฐ๋๋ค.
๋ํ ์ ์ํ ์ง์ฐ ์ด๋ ์ปจํธ๋กค๋ฌ๋ฅผ ํฌํจํ๋ ์ง๊ต ์ ํธ ๋ณด์ ๊ธฐ๋ 3 GHz ์ฟผ๋๋ฌ์ฒ ํด๋ญ ๊ฐ ์ต๋ 21.2 ps ์ ์คํ๋ฅผ 0.8 ps ๊น์ง ์ค์ผ ์ ์์ผ๋ฉฐ, ์ด ๋ 76.9 ns ์ ๊ต์ ์๊ฐ์ ๊ฐ๋๋ค. ์ ์ํ๋ ์ง๊ต ์ ํธ ๋ณด์ ๊ธฐ๋ 3 GHz ์์ 2.15 mW/GHz ์ ์ ๋ ฅ ํจ์จ์ ๊ฐ๋๋ค.A four-level pulse amplitude modulation (PAM-4) receiver, and a quadrature signal corrector (QSC) that generates quadrature clocks for memory interfaces is presented. Increasing IP traffic in data centers has increased the demand for high-speed and low-power memory interfaces. To satisfy this demand, PAM-4 signaling, which can increase data-rate without increasing clock and Nyquist frequency, is received considerable attention.
PAM- signaling has vertical which three times lower than non-return-to-zero (NRZ) signaling, which makes the clock-to-Q delay of the slicer in the decision feedback equalizer (DFE) increases. This makes the DFE difficult to satisfy the timing constraint. In this paper, by using a DFE with inverter-based summers, the clock-to-Q delay of the slicer can be reduced without increasing the power consumption of the slicers.
Also, the QSC using an adaptive delay gain controller can correct the skew between the quadrature clock with low skew and short correction time.
The prototype receiver including the DFE with the inverter-based summer and the QSC using the adaptive delay gain controller was fabricated in 65 nm CMOS process. The prototype chip can achieve a bit error rate (BER) of 10-12 at 24 Gb/s/pin, and at this time, an eye width of 100 mUI is secured. The efficiency of the receiver is 0.73 pJ/b. In addition, the QSC cna reduce the maximum 21.2 ps of skew between 3 GHz quadrature clocks to 0.8 ps and has a correction time of 76.9 ns. The efficiency of the QSC is 2.15 mW/GHz.ABSTRACT 1
CONTENTS 3
LIST OF FIGURES 5
LIST OF TABLE 9
CHAPTER 1 1
INTRODUCTION 1
1.1 MOTIVATION 1
1.2 PAM-4 SIGNALING 7
1.2.1 DESIGN CONSIDERATIONS ON PAM-4 RECEIVER 10
1.2.2 PRIOR WORKS 14
1.3 QUARTER-RATE ARCHITECTURE 18
1.3.1 DESIGN CONSIDERATION ON QUARTER-RATE ARCHITECTURE 20
1.3.2 PRIOR WORKS 25
1.4 SUMMARY 28
1.5 THESIS ORGANIZATION 30
CHAPTER 2 31
CONCEPTS OF DFE WITH INVERTER-BASED SUMMER 31
2.1 CONCEPTUAL ARCHITECTURE OF DFE WITH INVERTER-BASED SUMMER 32
2.2 DESIGN CONSIDERATION OF INVERTER-BASED SUMMER 37
CHAPTER 3 41
CONCEPTS OF QUADRATURE SIGNAL CORRECTOR USING ADAPTIVE DELAY GAIN CONTROLLER 41
3.1 OPERATION OF PROPOSED QUADRATURE SIGNAL CORRECTOR 42
3.2 LOOP FILTER INCLUDING ADAPTIVE DELAY GAIN CONTROLLER 45
CHAPTER 4 48
ARCHITECTURE AND IMPLEMENTATION 48
4.1 OVERALL ARCHITECTURE 49
4.2 ANALOG FRONT END 52
4.3 DECISION FEEDBACK EQUALIZER WITH INVERTER-BASED SUMMER 54
4.4 CLOCK PATH 62
4.5 QUADRATURE SIGNAL CORRECTOR WITH ADAPTIVE DELAY GAIN CONTROLLER 63
CHAPTER 5 70
EXPERIMENTAL RESULTS 70
5.1 EXPERIMENTAL SETUP 70
5.2 EXPERIMENTAL RESULTS 74
5.2.1 MEASUREMENT RESULTS OF PAM-4 RECEIVER WITH DECISION FEEDBACK EQUALIZER USING INVERTER-BASED SUMMER 74
5.2.2 MEASUREMENT RESULTS OF QUADRATURE SIGNAL CORRECTOR USING ADAPTIVE DELAY GAIN CONTROLLER 77
CHAPTER 6 83
CONCLUSION 83
BIBLIOGRAPHY 86๋ฐ
Proceedings of the 22nd Conference on Formal Methods in Computer-Aided Design โ FMCAD 2022
The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system verification. FMCAD provides a leading forum to researchers in academia and industry for presenting and discussing groundbreaking methods, technologies, theoretical results, and tools for reasoning formally about computing systems. FMCAD covers formal aspects of computer-aided system design including verification, specification, synthesis, and testing
ํต๊ณ์ ์ฃผํ์ ๊ฒ์ถ๊ธฐ ๊ธฐ๋ฐ ๊ธฐ์ค ์ฃผํ์๋ฅผ ์ฌ์ฉํ์ง ์๋ ํด๋ก ๋ฐ ๋ฐ์ดํฐ ๋ณต์ ํ๋ก์ ์ค๊ณ ๋ฐฉ๋ฒ๋ก
ํ์๋
ผ๋ฌธ(๋ฐ์ฌ) -- ์์ธ๋ํ๊ต๋ํ์ : ๊ณต๊ณผ๋ํ ์ ๊ธฐยท์ ๋ณด๊ณตํ๋ถ, 2022. 8. ์ ๋๊ท .In this thesis, a design of a high-speed, power-efficient, wide-range clock and data recovery (CDR) without a reference clock is proposed. A frequency acquisition scheme using a stochastic frequency detector (SFD) based on the Alexander phase detector (PD) is utilized for the referenceless operation. Pat-tern histogram analysis is presented to analyze the frequency acquisition behavior of the SFD and verified by simulation. Based on the information obtained by pattern histogram analysis, SFD using autocovariance is proposed. With a direct-proportional path and a digital integral path, the proposed referenceless CDR achieves frequency lock at all measurable conditions, and the measured frequency acquisition time is within 7ฮผs. The prototype chip has been fabricated in a 40-nm CMOS process and occupies an active area of 0.032 mm2. The proposed referenceless CDR achieves the BER of less than 10-12 at 32 Gb/s and exhibits an energy efficiency of 1.15 pJ/b at 32 Gb/s with a 1.0 V supply.๋ณธ ๋
ผ๋ฌธ์ ๊ธฐ์ค ํด๋ญ์ด ์๋ ๊ณ ์, ์ ์ ๋ ฅ, ๊ด๋์ญ์ผ๋ก ๋์ํ๋ ํด๋ญ ๋ฐ ๋ฐ์ดํฐ ๋ณต์ํ๋ก์ ์ค๊ณ๋ฅผ ์ ์ํ๋ค. ๊ธฐ์ค ํด๋ญ์ด ์๋ ๋์์ ์ํด์ ์๋ ์ฐ๋ ์์ ๊ฒ์ถ๊ธฐ์ ๊ธฐ๋ฐํ ํต๊ณ์ ์ฃผํ์ ๊ฒ์ถ๊ธฐ๋ฅผ ์ฌ์ฉํ๋ ์ฃผํ์ ํ๋ ๋ฐฉ์์ด ์ฌ์ฉ๋๋ค. ํต๊ณ์ ์ฃผํ์ ๊ฒ์ถ๊ธฐ์ ์ฃผํ์ ์ถ์ ์์์ ๋ถ์ํ๊ธฐ ์ํด ํจํด ํ์คํ ๊ทธ๋จ ๋ถ์ ๋ฐฉ๋ฒ๋ก ์ ์ ์ํ์๊ณ ์๋ฎฌ๋ ์ด์
์ ํตํด ๊ฒ์ฆํ์๋ค. ํจํด ํ์คํ ๊ทธ๋จ ๋ถ์์ ํตํด ์ป์ ์ ๋ณด๋ฅผ ๋ฐํ์ผ๋ก ์๊ธฐ๊ณต๋ถ์ฐ์ ์ด์ฉํ ํต๊ณ์ ์ฃผํ์ ๊ฒ์ถ๊ธฐ๋ฅผ ์ ์ํ๋ค. ์ง์ ๋น๋ก ๊ฒฝ๋ก์ ๋์งํธ ์ ๋ถ ๊ฒฝ๋ก๋ฅผ ํตํด ์ ์๋ ๊ธฐ์ค ํด๋ญ์ด ์๋ ํด๋ญ ๋ฐ ๋ฐ์ดํฐ ๋ณต์ํ๋ก๋ ๋ชจ๋ ์ธก์ ๊ฐ๋ฅํ ์กฐ๊ฑด์์ ์ฃผํ์ ์ ๊ธ์ ๋ฌ์ฑํ๋ ๋ฐ ์ฑ๊ณตํ์๊ณ , ๋ชจ๋ ๊ฒฝ์ฐ์์ ์ธก์ ๋ ์ฃผํ์ ์ถ์ ์๊ฐ์ 7ฮผs ์ด๋ด์ด๋ค. 40-nm CMOS ๊ณต์ ์ ์ด์ฉํ์ฌ ๋ง๋ค์ด์ง ์นฉ์ 0.032 mm2์ ๋ฉด์ ์ ์ฐจ์งํ๋ค. ์ ์ํ๋ ํด๋ญ ๋ฐ ๋ฐ์ดํฐ ๋ณต์ํ๋ก๋ 32 Gb/s์ ์๋์์ ๋นํธ์๋ฌ์จ 10-12 ์ดํ๋ก ๋์ํ์๊ณ , ์๋์ง ํจ์จ์ 32Gb/s์ ์๋์์ 1.0V ๊ณต๊ธ์ ์์ ์ฌ์ฉํ์ฌ 1.15 pJ/b์ ๋ฌ์ฑํ์๋ค.CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 THESIS ORGANIZATION 13
CHAPTER 2 BACKGROUNDS 14
2.1 CLOCKING ARCHITECTURES IN SERIAL LINK INTERFACE 14
2.2 GENERAL CONSIDERATIONS FOR CLOCK AND DATA RECOVERY 24
2.2.1 OVERVIEW 24
2.2.2 JITTER 26
2.2.3 CDR JITTER CHARACTERISTICS 33
2.3 CDR ARCHITECTURES 39
2.3.1 PLL-BASED CDR โ WITH EXTERNAL REFERENCE CLOCK 39
2.3.2 DLL/PI-BASED CDR 44
2.3.3 PLL-BASED CDR โ WITHOUT EXTERNAL REFERENCE CLOCK 47
2.4 FREQUENCY ACQUISITION SCHEME 50
2.4.1 TYPICAL FREQUENCY DETECTORS 50
2.4.1.1 DIGITAL QUADRICORRELATOR FREQUENCY DETECTOR 50
2.4.1.2 ROTATIONAL FREQUENCY DETECTOR 54
2.4.2 PRIOR WORKS 56
CHAPTER 3 DESIGN OF THE REFERENCELESS CDR USING SFD 58
3.1 OVERVIEW 58
3.2 PROPOSED FREQUENCY DETECTOR 62
3.2.1 MOTIVATION 62
3.2.2 PATTERN HISTOGRAM ANALYSIS 68
3.2.3 INTRODUCTION OF AUTOCOVARIANCE TO STOCHASTIC FREQUENCY DETECTOR 75
3.3 CIRCUIT IMPLEMENTATION 83
3.3.1 IMPLEMENTATION OF THE PROPOSED REFERENCELESS CDR 83
3.3.2 CONTINUOUS-TIME LINEAR EQUALIZER (CTLE) 85
3.3.3 DIGITALLY-CONTROLLED OSCILLATOR (DCO) 87
3.4 MEASUREMENT RESULTS 89
CHAPTER 4 CONCLUSION 99
APPENDIX A DETAILED FREQUENCY ACQUISITION WAVEFORMS OF THE PROPOSED SFD 100
BIBLIOGRAPHY 108
์ด ๋ก 122๋ฐ
Low-Power and Low-Noise Clock Generator for High-Speed ADCs
The rapid development of high-performance communication technologies reflects a clear trend in demanding requirements imposed on analog-to-digital converters (ADCs). Thus, it appears that these requirements imply higher frequencies not only for the input signal but also higher sampling frequencies, which translates into a higher sensitivity of the circuit to thermal noise and consequent increase in phase-noise. This arises as to the main purpose of this document, which will seek, as its main objective, the development of an architecture that allows the generation of multiple clock signals at high input frequencies with low jitter and low power dissipation to make ADCs more efficient and faster.
This dissertation proposes an architecture implemented by a Clock Buffer that converts a differential input signal into a single-ended output signal, a Digital Buffer that transforms a sine wave into a square wave, and finally a Multi Clock Phase Generator (MPCG), consisting of Shift Registers. Both architectures are implemented in 130 nm CMOS technology.
The architecture is powered by a LVDS signal with an amplitude of 200 mV and a frequency of 1 GHz, in order to output 8 square wave clock signals with an amplitude of 1.2 V and with a frequency of 125 MHz. The signals obtained at the output later will feed an architecture of 8 Time-Interleaved ADCs.
The total area of the implemented circuit is about 8054.3 ฮผm2, for a dissipated power of 5.3 mW and a jitter value of 1.13 ps.
This new architecture will be aimed at all types of entities that work with devices that are made up of high-speed performance ADCs, to improve the operation of these same devices, making the processing from a continuous signal to a discrete signal as efficiently as possible.O rรกpido desenvolvimento das tecnologias de comunicaรงรฃo de alto desempenho, reflete uma tendรชncia clara na exigรชncia dos requisitos impostos aos conversores analรณgico-digital (ADCs). Deste modo, verifica-se que estes requisitos implicam elevadas frequรชncias nรฃo sรณ sinal de entrada, como tambรฉm frequรชncias elevadas de amostragem o que se traduz numa maior sensibilidade do circuito ao ruรญdo tรฉrmico e consequente aumento ruรญdo de fase. Esta problemรกtica, surge como propรณsito principal deste documento, no qual se procurarรก, como objetivo principal, o desenvolvimento de uma arquitetura que permita gerar mรบltiplos sinais de relรณgio a altas frequรชncias de entrada e perรญodos de amostragem, com um baixo jitter e baixa energia consumida de forma a tornar mais eficiente e rรกpido o funcionamento de ADCs. Ruido tรฉrmico.
Esta dissertaรงรฃo propรตe uma arquitetura composta por um amplificador de sinal de relรณgio que converte o duplo sinal de entrada num รบnico sinal de saรญda, um amplificador digital que transforma uma onda sinusoidal numa onda quadrada e por fim um gerador de fase mรบltipla de sinais de relรณgio (MPCG), constituรญdo por registos de deslocamento. Ambas as arquiteturas sรฃo implementadas em tecnologia CMOS de 130 nm.
A arquitetura รฉ alimentada com um sinal LVDS de 200 mV de amplitude e com uma frequรชncia de 1 GHz, de forma a obter ร saรญda 8 sinais de relรณgio de onda quadrada com uma amplitude de 1,2 V e com 125 MHz de frequรชncia. Os sinais obtidos ร saรญda posteriormente alimentarรฃo uma arquitetura de 8 canais com multiplexagem temporal.
A รกrea total do circuito implementado รฉ cerca de 8054,3 ฮผm2, para uma potรชncia dissipada de 5,3 mW e para um valor de jitter de 1,13 ps.
Esta nova arquitetura serรก direcionada para todo o tipo de entidades que trabalham com dispositivos que sรฃo constituรญdos por ADCs de alta velocidade de desempenho, de forma a poder melhorar o funcionamento desses mesmos dispositivos, tornando o processamento de sinal continuo para sinal discreto o mais eficiente possรญvel
Network-on-Chip
Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoCโits research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems
Optical Communication
Optical communication is very much useful in telecommunication systems, data processing and networking. It consists of a transmitter that encodes a message into an optical signal, a channel that carries the signal to its desired destination, and a receiver that reproduces the message from the received optical signal. It presents up to date results on communication systems, along with the explanations of their relevance, from leading researchers in this field. The chapters cover general concepts of optical communication, components, systems, networks, signal processing and MIMO systems. In recent years, optical components and other enhanced signal processing functions are also considered in depth for optical communications systems. The researcher has also concentrated on optical devices, networking, signal processing, and MIMO systems and other enhanced functions for optical communication. This book is targeted at research, development and design engineers from the teams in manufacturing industry, academia and telecommunication industries
Design of Readout Electronics for the DEEP Particle Detector
Along with electromagnetic radiation, the Sun also emits a constant stream of charged particles in the form of solar wind. When these particles enter Earthโs atmosphere through a process known as particle precipitation, they can through a series of chemical reactions produce N Ox and HOx gases. These gases are greenhouse gases and deplete the ozone in the mesosphere and upper stratosphere. It is important to quantify the rate of production of these gases to model the potential climate impact. Existing particle detectors in space are suboptimal because they cannot determine the energy flux and pitch angle distribution of precipitating particles. The primary scientific objective of the DEEP project is to design a particle detector instrument that is specifically designed for particle precipitation measurements. This thesis investigates different data acquisition schemes for handling the signal from a pixel detector. The chosen approach is measuring the width of a shaped pulse to quantify the energy of the particle. Known as Time-over-Threshold, a detector circuit board is designed featuring high-speed comparators as threshold discriminators and the NG-MEDIUM FPGA from NanoXplore to implement the data acquisition. Digitizing the comparator pulse width is done with a Time-to-Digital converter (TDC) implemented in the FPGA fabric. Since the difference in pulse width is small for different energies, a high conversion resolution is required. Two high-resolution TDCs are designed and compared, both of which feature a digital counter and a method of interpolating the counter clock period. The first interpolation method applies the use of a multitapped delay line implemented with hard carry chain resources, and the second method oversamples the input with several equally off-phase sampling clocks. A resolution of 302 ps and a differential non-linearity of 3.26 was achieved with the delay line TDC clocked at 100 MHz. An automatic statistical calibration scheme is included to determine the actual delays of the delay line, utilizing a second asynchronous clock to generate uniformly distributed hits. The asynchronous oversampler resolution is clock frequency dependent and provides a 4-fold improvement to the clock period. The differential nonlinearity approaches zero with close matching of the off-phase clocks and operating frequency. A complete firmware design for the data acquisition and rocket telemetry of the detector is proposed and demonstrated. A simulation of the firmware utilizing each TDC topology is conducted and the delay line TDC is demonstrated to be the most accurate at all operating frequencies and thus the recommended TDC for the DEEP data acquisition.Masteroppgave i fysikkPHYS399MAMN-PHY
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