IDPAL – A Partially-Adiabatic Energy-Efficient Logic Family: Theory and Applications to Secure Computing

Low-power circuits and issues associated with them have gained a significant amount of attention in recent years due to the boom in portable electronic devices. Historically, low-power operation relied heavily on technology scaling and reduced operating voltage, however this trend has been slowing down recently due to the increased power density on chips. This dissertation introduces a new very-low power partially-adiabatic logic family called Input-Decoupled Partially-Adiabatic Logic (IDPAL) with applications in low-power circuits. Experimental results show that IDPAL reduces energy usage by 79% compared to equivalent CMOS implementations and by 25% when compared to the best adiabatic implementation. Experiments ranging from a simple buffer/inverter up to a 32-bit multiplier are explored and result in consistent energy savings, showing that IDPAL could be a viable candidate for a low-power circuit implementation. This work also shows an application of IDPAL to secure low-power circuits against power analysis attacks. It is often assumed that encryption algorithms are perfectly secure against attacks, however, most times attacks using side channels on the hardware implementation of an encryption operation are not investigated. Power analysis attacks are a subset of side channel attacks and can be implemented by measuring the power used by a circuit during an encryption operation in order to obtain secret information from the circuit under attack. Most of the previously proposed solutions for power analysis attacks use a large amount of power and are unsuitable for a low-power application. The almost-equal energy consumption for any given input in an IDPAL circuit suggests that this logic family is a good candidate for securing low-power circuits again power analysis attacks. Experimental results ranging from small circuits to large multipliers are performed and the power-analysis attack resistance of IDPAL is investigated. Results show that IDPAL circuits are not only low-power but also the most secure against power analysis attacks when compared to other adiabatic low-power circuits. Finally, a hybrid adiabatic-CMOS microprocessor design is presented. The proposed microprocessor uses IDPAL for the implementation of circuits with high switching activity (e.g. ALU) and CMOS logic for other circuits (e.g. memory, controller). An adiabatic-CMOS interface for transforming adiabatic signals to square-wave signals is presented and issues associated with a hybrid implementation and their solutions are also discussed

Ultralow-Power and Secure S-Box Circuit Using FinFET Based ECRL Adiabatic Logic

Advanced Encryption Standard (AES) is the widely used technique in critical cyber security applications. In AES architecture S-box is the most important block. However, the power consumed by      S-box is 75% of the total AES design. The   S-box is also prone to Differential Power Analysis (DPA) attack which is one of the most threatening types of attacks in cryptographic systems. In this paper, a     three-stage positive polarity Reed-Muller (PPRM) S-box is implemented with 45nm FinFET using Efficient Charge Recovery Logic (ECRL) to reduce power consumption. The simulation results indicate up to 66% power savings for FinFET based S-box as compared to CMOS design. Further, the FinFET ECRL 8-bit     S-box circuit is evaluated for transitional energy fluctuations and peak current traces to compare its resistance against side-channel attacks. The lower energy variations and uniform current trace exhibit the improved security performance of the circuit to withstand DPA and Differential Electromagnetic Radiation Attacks (DEMA)

IDPAL - Input Decoupled Partially Adiabatic Logic: Implementation and Examination

This thesis presents the experimental results of a four-phase IDPAL eight-input exclusive-OR gate. The following problems with IDPAL are addressed: multistage circuits malfunctioning, simulation convergence anomalies, and inferring input information through the power clock current. EPAD MOSFETs, which provide a low threshold voltage, are shown to be unsuccessful in correcting the malfunctioning behavior of multilayer circuits. A solution to multilayer IDPAL circuits malfunctioning, called IDPAL with discharge, is shown. The differences between simulation waveforms produced by LTspice and the experimental circuits recorded by a Tektronix’s Oscilloscope are investigated. IDPAL is implemented and analyzed using ALD MOSFETs for the following adiabatic families: 2N-2P, IDPAL, and IDPAL with discharge

Adiabatic low power CMOS.

by Kelvin Cheung Ka Wai.Thesis submitted in: June 1997.Thesis (M.Phil.)--Chinese University of Hong Kong, 1998.Includes bibliographical references.ACKNOWLEDGEMENTS --- p.iABSTRACT --- p.iiTABLE OF CONTENTS --- p.iiiLIST OF FIGURES --- p.viTIST OF TABLES --- p.viiiChapter 1. --- INTRODUCTION --- p.1-1Chapter 1.1 --- Introduction --- p.1-1Chapter 1.2 --- Objective --- p.1-1Chapter 1.3 --- Static CMOS Logic and Dynamic Logic --- p.1-1Chapter 1.3.1 --- static CMOS logic circuit --- p.1-1Chapter 1.3.2 --- Dynamic logic --- p.1-2Chapter 1.4 --- Power Consumption in Static CMOS Integrated Circuit --- p.1-4Chapter 1.4.1 --- Static power dissipation --- p.1 -4Chapter 1.4.2 --- Dynamic power dissipation --- p.1 -6Chapter 1.4.2.1 --- Short circuit current --- p.1 -6Chapter 1.4.2.2 --- Charging and discharging of load capacitances --- p.1-6Chapter 1.4.2.3 --- Total power consumption --- p.1-8Chapter 1.5 --- Adiabatic Logic --- p.1-8Chapter 1.5.1 --- Low power electronics --- p.1-8Chapter 1.5.2 --- History of adiabatic logic --- p.1 -9Chapter 1.6 --- Resources --- p.1-10Chapter 1.6.1 --- Computing instrument --- p.1-10Chapter 1.6.2 --- CAD tools --- p.1-10Chapter 1.6.3 --- Fabrication --- p.1-11Chapter 1.7 --- Organisation of the Thesis --- p.1-11Chapter 2. --- BACKGROUND THEORIES --- p.2-1Chapter 2.1 --- Limit of energy dissipation --- p.2-1Chapter 2.2 --- Reversible Electronics --- p.2-1Chapter 2.2.1 --- Reversibility --- p.2-1Chapter 2.2.2 --- Adiabatic Switching --- p.2-3Chapter 2.2.2.1 --- Conventional Charging --- p.2-3Chapter 2.2.2.2 --- Adiabatic Charging --- p.2-4Chapter 2.2.3 --- Reversible devices --- p.2-5Chapter 2.3 --- Compatibility to CMOS Logic --- p.2-6Chapter 3. --- ADIABATIC QUASI-STATIC CMOS --- p.3-1Chapter 3.1 --- Swinging between 0 and 1 by Harmonic Motion --- p.3-1Chapter 3.1.1 --- Starting from a simple pendulum --- p.3-1Chapter 3.1.2 --- Inductor-capacitor oscillator --- p.3-2Chapter 3.2 --- Redistribution of Charge --- p.3-3Chapter 3.3 --- Adiabatic Quasi-static Logic --- p.3-4Chapter 3.3.1 --- False reversible inverter --- p.3-4Chapter 3.3.2 --- Adiabatic inverter --- p.3-5Chapter 3.3.3 --- Effective capacitance --- p.3-7Chapter 3.3.4 --- Logic alignment --- p.3-8Chapter 3.3.5 --- Cascading the adiabatic inverters --- p.3-10Chapter 3.3.5.1 --- Compensated cascading --- p.3-10Chapter 3.3.5.2 --- Balanced cascading --- p.3-11Chapter 3.4 --- Frequency Control --- p.3-12Chapter 3.5 --- Compatibility of AqsCMOS with Static CMOS Logic --- p.3-13Chapter 4. --- ADIABATIC QUASI-STATIC CMOS INVERTERS --- p.4-1Chapter 4.1 --- Design --- p.4-1Chapter 4.1.1 --- Realisation of current direction control device --- p.4-1Chapter 4.1.2 --- Implementation of AqsCMOS inverter by current direction control device --- p.4-2Chapter 4.1.3 --- Layout --- p.4-3Chapter 4.1.3.1 --- Horizontal Transistor Diode --- p.4-3Chapter 4.1.3.2 --- Transistor pair --- p.4-9Chapter 4.2 --- Capacitance Calculation --- p.4-9Chapter 4.2.1 --- Non-switching device --- p.4-10Chapter 4.2.2 --- Switching device --- p.4-11Chapter 4.3 --- Clocking Scheme --- p.4-13Chapter 4.4 --- Energy Loss of AqsCMOS inverter --- p.4-14Chapter 5. --- ADIABATIC CLOCKS GENERATOR --- p.5-1Chapter 5.1 --- Introduction --- p.5-1Chapter 5.2 --- Full Adiabatic Clocks Generator --- p.5-1Chapter 5.2.1 --- Sizes of the transistors used --- p.5-2Chapter 5.2.2 --- Energy consumption of full adiabatic clocks generator --- p.5-3Chapter 5.3 --- Half Adiabatic Clocks Generator --- p.5-4Chapter 5.3.1 --- Transistor sizing --- p.5-5Chapter 5.3.2 --- Energy consumption of the half adiabatic clock generator --- p.5-5Chapter 5.3.3 --- Weakness of the half adiabatic clocks generator --- p.5-6Chapter 5.4 --- Automatic Adiabatic Clocks Generator --- p.5-6Chapter 5.4.1 --- Operation of automatic adiabatic clocks generator --- p.5-7Chapter 5.4.2 --- Energy consumption of automatic adiabatic clocks generator --- p.5-9Chapter 6. --- EVALUATION --- p.6-1Chapter 6.1 --- Introduction --- p.6-1Chapter 6.2 --- Simulation Results --- p.6-1Chapter 6.2.1 --- Adiabatic clocks generators --- p.6-1Chapter 6.2.2 --- Adiabatic quasi-static CMOS inverters --- p.6-4Chapter 6.2.2.1 --- Functional evaluation --- p.6-4Chapter 6.2.2.2 --- Performance evaluation --- p.6-6Chapter 6.3 --- Test Circuit - Pendulum --- p.6-8Chapter 6.3.1 --- Layout --- p.6-8Chapter 6.3.2 --- Test circuit of pendulum --- p.6-10Chapter 6.3.3 --- Module 1 - Full adiabatic clocks generator (fclk) --- p.6-11Chapter 6.3.4 --- Module 2 - Half adiabatic clocks generator (hclk) --- p.6-13Chapter 6.3.5 --- Module 3 to 5- Adiabatic inverter chains --- p.6-14Chapter 6.3.5.1 --- DC characteristics --- p.6-14Chapter 6.3.5.2 --- AC characteristics --- p.6-14Chapter 6.3.6 --- Power dissipation --- p.6-17Chapter 7 --- CONCLUSIONS --- p.7-1Chapter 7.1 --- Introduction --- p.7-1Chapter 7.2 --- Design --- p.7-1Chapter 7.2.1 --- Adiabatic quasi-static CMOS logic --- p.7-1Chapter 7.2.2 --- Adiabatic quasi-static CMOS inverters --- p.7-2Chapter 7.2.3 --- Adiabatic clocks generator --- p.7-2Chapter 7.3 --- Function --- p.7-3Chapter 7.4 --- Power Dissipation --- p.7-3Chapter 7.5 --- Discussion --- p.7-3Chapter 7.6 --- Further Development --- p.7-3Chapter 7.7 --- Conclusion --- p.7-4Chapter 8. --- REFERENCES --- p.8-1APPENDIX I TABLE OF PTN LAYOUT PENDULUM --- p.I-1APPENDIX II PHOTOGRAPHS OF PENDULUM --- p.II-

An Adiabatic Capacitive Artificial Neuron With RRAM-Based Threshold Detection for Energy-Efficient Neuromorphic Computing

In the quest for low power, bio-inspired computation both memristive and memcapacitive-based Artificial Neural Networks (ANN) have been the subjects of increasing focus for hardware implementation of neuromorphic computing. One step further, regenerative capacitive neural networks, which call for the use of adiabatic computing, offer a tantalising route towards even lower energy consumption, especially when combined with `memimpedace' elements. Here, we present an artificial neuron featuring adiabatic synapse capacitors to produce membrane potentials for the somas of neurons; the latter implemented via dynamic latched comparators augmented with Resistive Random-Access Memory (RRAM) devices. Our initial 4-bit adiabatic capacitive neuron proof-of-concept example shows 90% synaptic energy saving. At 4 synapses/soma we already witness an overall 35% energy reduction. Furthermore, the impact of process and temperature on the 4-bit adiabatic synapse shows a maximum energy variation of 30% at 100 degree Celsius across the corners without any functionality loss. Finally, the efficacy of our adiabatic approach to ANN is tested for 512 & 1024 synapse/neuron for worst and best case synapse loading conditions and variable equalising capacitance's quantifying the expected trade-off between equalisation capacitance and range of optimal power-clock frequencies vs. loading (i.e. the percentage of active synapses).Comment: This work has been accepted to the IEEE TCAS-

Adiabatic Logic Design for Low Power VLSI Applications

A conventional CMOS logic circuit design approach depends upon charging the output capacitive nodes to the supply voltage or discharging it to the ground. This is one of the most used methods in VLSI designs. There are various techniques to design low power circuits both at system level as well as at circuit level to reduce power consumption. One of the major source of power dissipation is the charging and discharging of capacitor. Every time when a capacitor is discharged to ground, an amount of energy = ½ C stored in the capacitor is lost. We can reduce this power dissipation by restoring this energy to the source instead of discharging to the ground. Another way of reducing the power dissipation is to design the circuit in such a way that the charging of the capacitive node takes place very slowly. It has been observed that by charging the capacitor slowly, the energy require is lesser than faster charging method. Adiabatic circuits use the above two methods viz. slow charging of capacitor and discharging, and recycling of charge to minimize the power consumed. Several Adiabatic designs have been designed and tested in this paper. Most of them achieve significant power savings in comparison to conventional CMOS designs. The major drawbacks of these circuits include complex design for achieving simple operations, requirement of multiple clocks and requirement of complimentary input signals for controlling the charging and discharging process. The Current work is based on an existing adiabatic logic style known as PFAL (Positive Feedback Adiabatic Logic) and ECRL (Energy Efficient Charge Recovery Logic) which are simple and doesn’t require complimentary signals or complex clocking. “ A simulative investigation on the proposed 1-bit full adder has been implemented with the proposed technique and hence compared with standard CMOS, Positive Feedback Adiabatic Logic (PFAL), Static Energy Recovery Full Adder (SERF), 8T Full Adder and 9T Full Adder respectively. We compared all the designs and achieved a significant power saving to the extent of 40% in case of proposed technique as compared to CMOS logic in 50 to 200MHz transition frequency range. Later in this paper I have implemented the carry look-ahead adder based on adiabatic logic and got a faster response up to 100ps as compared to Full adder counterpart. A comparative result has also been shown by a graph which represents the least power dissipation of proposed technique. In this paper all circuits are analysed in terms of power using 90nm technology and simulated using cadence virtuoso and Tanner EDA

Comparative Study on Performance and Variation Tolerance of Low Power Circuit

The demand for low-power electronic devices is increasing rapidly in current VLSI technology. Instead of conventional CMOS circuit operating at nominal supply voltage, several kinds of circuits are brought about with the goal of reducing power consumption. This research is mainly focused on evaluating performance, power and variation tolerance of near/sub-threshold computing and adiabatic logic circuits. Arithmetic logic units (ALUs) are designed with 15nm FinFET process technologies for these circuit styles. The evaluation is carried out by simulations on these ALU designs. The variation model considers ambient temperature variations and power supply fluctuations that emulate wireless sensor node applications. The results shows that conventional static CMOS circuit operating in near-threshold region exhibits similar power efficiency with adiabatic logic circuit operating in the same region, while at the same time it bears better temperature and voltage variation tolerance in most of the cases. The study results provide helpful guidance to low-power electronic system designs

A Charge-Recycling Scheme and Ultra Low Voltage Self-Startup Charge Pump for Highly Energy Efficient Mixed Signal Systems-On-A-Chip

The advent of battery operated sensor-based electronic systems has provided a pressing need to design energy-efficient, ultra-low power integrated circuits as a means to improve the battery lifetime. This dissertation describes a scheme to lower the power requirement of a digital circuit through the use of charge-recycling and dynamic supply-voltage scaling techniques. The novel charge-recycling scheme proposed in this research demonstrates the feasibility of operating digital circuits using the charge scavenged from the leakage and dynamic load currents inherent to digital design. The proposed scheme efficiently gathers the “ground-bound” charge into storage capacitor banks. This reclaimed charge is then subsequently recycled to power the source digital circuit. The charge-recycling methodology has been implemented on a 12-bit Gray-code counter operating at frequencies of less than 50 MHz. The circuit has been designed in a 90-nm process and measurement results reveal more than 41% reduction in the average energy consumption of the counter. The total energy savings including the power consumed for the generation of control signals aggregates to an average of 23%. The proposed methodology can be applied to an existing digital path without any design change to the circuit but with only small loss to the performance. Potential applications of this scheme are described, specifically in wide-temperature dynamic power reduction and as a source for energy harvesters. The second part of this dissertation deals with the design and development of a self-starting, ultra-low voltage, switched-capacitor (SC) DC-DC converter that is essential to an energy harvesting system. The proposed charge-pump based SC-converter operates from 125-mV input and thus enables battery-less operation in ultra-low voltage energy harvesters. The charge pump does not require any external components or expensive post-fabrication processing to enable low-voltage operation. This design has been implemented in a 130-nm CMOS process. While the proposed charge pump provides significant efficiency enhancement in energy harvesters, it can also be incorporated within charge recycling systems to facilitate adaptable charge-recycling levels. In total, this dissertation provides key components needed for highly energy-efficient mixed signal systems-on-a-chip

ENERGY-EFFICIENT AND SECURE HARDWARE FOR INTERNET OF THINGS (IoT) DEVICES

Internet of Things (IoT) is a network of devices that are connected through the Internet to exchange the data for intelligent applications. Though IoT devices provide several advantages to improve the quality of life, they also present challenges related to security. The security issues related to IoT devices include leakage of information through Differential Power Analysis (DPA) based side channel attacks, authentication, piracy, etc. DPA is a type of side-channel attack where the attacker monitors the power consumption of the device to guess the secret key stored in it. There are several countermeasures to overcome DPA attacks. However, most of the existing countermeasures consume high power which makes them not suitable to implement in power constraint devices. IoT devices are battery operated, hence it is important to investigate the methods to design energy-efficient and secure IoT devices not susceptible to DPA attacks. In this research, we have explored the usefulness of a novel computing platform called adiabatic logic, low-leakage FinFET devices and Magnetic Tunnel Junction (MTJ) Logic-in-Memory (LiM) architecture to design energy-efficient and DPA secure hardware. Further, we have also explored the usefulness of adiabatic logic in the design of energy-efficient and reliable Physically Unclonable Function (PUF) circuits to overcome the authentication and piracy issues in IoT devices. Adiabatic logic is a low-power circuit design technique to design energy-efficient hardware. Adiabatic logic has reduced dynamic switching energy loss due to the recycling of charge to the power clock. As the first contribution of this dissertation, we have proposed a novel DPA-resistant adiabatic logic family called Energy-Efficient Secure Positive Feedback Adiabatic Logic (EE-SPFAL). EE-SPFAL based circuits are energy-efficient compared to the conventional CMOS based design because of recycling the charge after every clock cycle. Further, EE-SPFAL based circuits consume uniform power irrespective of input data transition which makes them resilience against DPA attacks. Scaling of CMOS transistors have served the industry for more than 50 years in providing integrated circuits that are denser, and cheaper along with its high performance, and low power. However, scaling of the transistors leads to increase in leakage current. Increase in leakage current reduces the energy-efficiency of the computing circuits,and increases their vulnerability to DPA attack. Hence, it is important to investigate the crypto circuits in low leakage devices such as FinFET to make them energy-efficient and DPA resistant. In this dissertation, we have proposed a novel FinFET based Secure Adiabatic Logic (FinSAL) family. FinSAL based designs utilize the low-leakage FinFET device along with adiabatic logic principles to improve energy-efficiency along with its resistance against DPA attack. Recently, Magnetic Tunnel Junction (MTJ)/CMOS based Logic-in-Memory (LiM) circuits have been explored to design low-power non-volatile hardware. Some of the advantages of MTJ device include non-volatility, near-zero leakage power, high integration density and easy compatibility with CMOS devices. However, the differences in power consumption between the switching of MTJ devices increase the vulnerability of Differential Power Analysis (DPA) based side-channel attack. Further, the MTJ/CMOS hybrid logic circuits which require frequent switching of MTJs are not very energy-efficient due to the significant energy required to switch the MTJ devices. In the third contribution of this dissertation, we have investigated a novel approach of building cryptographic hardware in MTJ/CMOS circuits using Look-Up Table (LUT) based method where the data stored in MTJs are constant during the entire encryption/decryption operation. Currently, high supply voltage is required in both writing and sensing operations of hybrid MTJ/CMOS based LiM circuits which consumes a considerable amount of energy. In order to meet the power budget in low-power devices, it is important to investigate the novel design techniques to design ultra-low-power MTJ/CMOS circuits. In the fourth contribution of this dissertation, we have proposed a novel energy-efficient Secure MTJ/CMOS Logic (SMCL) family. The proposed SMCL logic family consumes uniform power irrespective of data transition in MTJ and more energy-efficient compared to the state-of-art MTJ/ CMOS designs by using charge sharing technique. The other important contribution of this dissertation is the design of reliable Physical Unclonable Function (PUF). Physically Unclonable Function (PUF) are circuits which are used to generate secret keys to avoid the piracy and device authentication problems. However, existing PUFs consume high power and they suffer from the problem of generating unreliable bits. This dissertation have addressed this issue in PUFs by designing a novel adiabatic logic based PUF. The time ramp voltages in adiabatic PUF is utilized to improve the reliability of the PUF along with its energy-efficiency. Reliability of the adiabatic logic based PUF proposed in this dissertation is tested through simulation based temperature variations and supply voltage variations