LOW PHASE NOISE CMOS PLL FREQUENCY SYNTHESIZER DESIGN AND ANALYSIS

The phase-locked loop (PLL) frequency synthesizer is a critical device of wireless transceivers. It works as a local oscillator (LO) for frequency translation and channel selection in the transceivers but suffers phase noise including reference spurs. In this dissertation for lowing phase noise and power consumption, efforts are placed on the new design of PLL components: VCOs, charge pumps and sigma delta modulators. Based on the analysis of the VCO phase noise generation mechanism and improving on the literature results, a design-oriented phase noise model for a complementary cross-coupled LC VCO is provided. The model reveals the relationship between the phase noise performance and circuit design parameters. Using this phase noise model, an optimized 2GHz low phase noise CMOS LC VCO is designed, simulated and fabricated. The theoretical analysis results are confirmed by the simulation and experimental results. With this VCO phase noise model, we also design a low phase noise, low gain wideband VCO with the typical VCO gain around 100MHz/V. Improving upon literature results, a complete quantitative analysis of reference spur is given in this dissertation. This leads to a design of a charge pump by using a negative feedback circuit and replica bias to reduce the current mismatch which causes the reference spur. In addition, low-impedance charge/discharge paths are provided to overcome the charge pump current glitches which also cause PLL spurs. With a large bit-width high order sigma delta modulator, the fractional-N PLL has fine frequency resolution and fast locking time. Based on an analysis of sigma delta modulator models introduced in this dissertation, a 3rd-order MASH 1-1-1 digital sigma delta modulator is designed. Pipelining techniques and true single phase clock (TSPC) techniques are used for saving power and area. Included is the design of a fully integrated 2.4GHz §¢ fractional-N CMOS PLL frequency synthesizer. It takes advantage of a sigma delta modulator to get a very fine frequency resolution and a relatively large loop bandwidth. This frequency synthesizer is a 4th-order charge pump PLL with 26MHz reference frequency. The loop bandwidth is about 150KHz, while the whole PLL phase noise is about -120dBc/Hz at 1MHz frequency offset

Direct Conversion RF Front-End Implementation for Ultra-Wideband (UWB) and GSM/WCDMA Dual-Band Applications in Silicon-Based Technologies

This dissertation focuses on wideband circuit design and implementation issues up to 10GHz based on the direct conversion architecture in the CMOS and SiGe BiCMOS technologies. The dissertation consists of two parts: One, implementation of a RF front-end receiver for an ultra-wideband system and, two, implementation of a local oscillation (LO) signal for a GSM/WCDMA multiband application. For emerging ultra-wideband (UWB) applications, the key active components in the RF front-end receiver were designed and implemented in 0.18um SiGe BiCMOS process. The design of LNA, which is the critical circuit block for both systems, was analyzed in terms of noise, linearity and group delay variation over an extemely wide bandwidth. Measurements are demonstrated for an energy-thrifty UWB receiver based on an MB-OFDM system covering the full FCC-allowed UWB frequency range. For multiband applications such as a GSM/WCDMA dual-band application, the design of wideband VCO and various frequency generation blocks are investigated as alternatives for implementation of direct conversion architecture. In order to reduce DC-offset and LO pulling phenomena that degrade performance in a typical direct conversion scheme, an innovative fractional LO signal generator was implemented in a standard CMOS process. A simple analysis is provided for the loop dynamics and operating range of the design as well as for the measured results of the factional LO signal generator.Ph.D.Committee Chair: Dr. Laskar, Joy; Committee Member: Dr. Cressler, John; Committee Member: Dr. Kohl, Paul; Committee Member: Dr. Papapolymerou, John; Committee Member: Dr. Scott, Waymon

Circuits and Systems for On-Chip RF Chemical Sensors and RF FDD Duplexers

Integrating RF bio-chemical sensors and RF duplexers helps to reduce cost and area in the current applications. Furthermore, new applications can exist based on the large scale integration of these crucial blocks. This dissertation addresses the integration of RF bio-chemical sensors and RF duplexers by proposing these initiatives. A low power integrated LC-oscillator-based broadband dielectric spectroscopy (BDS) system is presented. The real relative permittivity ε’r is measured as a shift in the oscillator frequency using an on-chip frequency-to-digital converter (FDC). The imaginary relative permittivity ε”r increases the losses of the oscillator tank which mandates a higher dc biasing current to preserve the same oscillation amplitude. An amplitude-locked loop (ALL) is used to fix the amplitude and linearize the relation between the oscillator bias current and ε”r. The proposed BDS system employs a sensing oscillator and a reference oscillator where correlated double sampling (CDS) is used to mitigate the impact of flicker noise, temperature variations and frequency drifts. A prototype is implemented in 0.18 µm CMOS process with total chip area of 6.24 mm^2 to operate in 1-6 GHz range using three dual bands LC oscillators. The achieved standard deviation in the air is 2.1 ppm for frequency reading and 110 ppm for current reading. A tunable integrated electrical balanced duplexer (EBD) is presented as a compact alternative to multiple bulky SAW and BAW duplexers in 3G/4G cellular transceivers. A balancing network creates a replica of the transmitter signal for cancellation at the input of a single-ended low noise amplifier (LNA) to isolate the receive path from the transmitter. The proposed passive EBD is based on a cross-connected transformer topology without the need of any extra balun at the antenna side. The duplexer achieves around 50 dB TX-RX isolation within 1.6-2.2 GHz range up to 22 dBm. The cascaded noise figure of the duplexer and LNA is 6.5 dB, and TX insertion loss (TXIL) of the duplexer is about 3.2 dB. The duplexer and LNA are implemented in 0.18 µm CMOS process and occupy an active area of 0.35 mm^2

Design and Implementation of a Low‐Power Wireless Respiration Monitoring Sensor

Wireless devices for monitoring of respiration activities can play a major role in advancing modern home-based health care applications. Existing methods for respiration monitoring require special algorithms and high precision filters to eliminate noise and other motion artifacts. These necessitate additional power consuming circuitry for further signal conditioning. This dissertation is particularly focused on a novel approach of respiration monitoring based on a PVDF-based pyroelectric transducer. Low-power, low-noise, and fully integrated charge amplifiers are designed to serve as the front-end amplifier of the sensor to efficiently convert the charge generated by the transducer into a proportional voltage signal. To transmit the respiration data wirelessly, a lowpower transmitter design is crucial. This energy constraint motivates the exploration of the design of a duty-cycled transmitter, where the radio is designed to be turned off most of the time and turned on only for a short duration of time. Due to its inherent duty-cycled nature, impulse radio ultra-wideband (IR-UWB) transmitter is an ideal candidate for the implementation of a duty-cycled radio. To achieve better energy efficiency and longer battery lifetime a low-power low-complexity OOK (on-off keying) based impulse radio ultra-wideband (IR-UWB) transmitter is designed and implemented using standard CMOS process. Initial simulation and test results exhibit a promising advancement towards the development of an energy-efficient wireless sensor for monitoring of respiration activities

DDR5 클락 버퍼를 위한 LC PLL의 설계

학위논문(석사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022. 8. 정덕균.This thesis describes a wide-range, fast-locking LC PLL for DDR5 clock buffer application. To operate LC PLL at wide range of input frequency, proposed PLL uses LC VCO with 28GHz center frequency and calculates appropriate division ratio of programmable divider for certain input frequen-cy at transient state. Calculating division ratio is achieved by using integer counter and fractional counter, detecting frequency of input clock at transient state. After calculating division ratio, proposed PLL operates as 3rd order charge pump PLL with optimum current value to lock fast. Proposed PLL is described with Systemverilog and simulation results shows that proposed LC PLL operates at 1 ~ 4.2GHz input frequency, while successfully acquires to lock at under 1μs. Also, LC-VCO is designed in a 40nm CMOS and simulation results shows that tuning range of VCO is ±9.25% with respect to center frequency of 28.2GHz, and VCO dissipates 26.4mW and phase noise is –104.86dBc/Hz at 1MHz offset, operating at center fre-quency with 1.1V supply voltage.본 논문은 DDR5 Clock Buffer를 위한, 넓은 범위에서 빠르게 락을 하는 LC PLL에 대해서 설명한다. 넓은 범위의 입력 주파수에서 LC PLL을 동작하기 위해, 제안한 PLL은 28GHz가 중심 주파수인 LC VCO을 사용하여, 과도 상태에서 특정 입력 주파수에 알맞는 프로그램 가능한divider의 제수를 계산한다. 제수의 계산은 과도 상태에서 입력 클락의 주파수를 감지하는 정수 카운터와 소수 카운터를 통해 이루어진다. 제수의 계산 이후, 제안한 PLL은 빠르게 락을 하기 위한 최적의 전류 값으로 3차의 Charge pump PLL로 동작한다. 제안한 PLL은 systemverilog로 기술되었고 시뮬레이션 결과 제안한 LC PLL은 1 ~ 4.2GHz의 입력주파수에서 동작하며, 1us 이내에서 성공적으로 락을 한다. 또한, LC-VCO가 40nm CMOS 공정에서 설계되었고, 시뮬레이션 결과 VCO의 튜닝 범위가 중심 주파수 28.2GHz을 기준으로 ±9.25%이고, 중심 주파수와 1.1V 공급 전압에서 26.4mW의 전력을 소모하고, phase noise가 1MHz 오프셋에서 -104.86dBc/Hz임을 확인할 수 있었다.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 3 CHAPTER 2 BACKGROUND ON LC PLL 4 2.1 BASIS OF PLL 4 2.2 FREQUENCY RANGE AND LOCK TIME OF PLL 11 2.2.1 FREQUENCY RANGE 11 2.2.2 LOCK TIME 13 2.3 BASIS OF LC VCO 15 CHAPTER 3 DESIGN OF LC PLL FOR DDR5 CLOCK BUFFER 18 3.1 DESIGN CONSIDERATION 18 3.2 OVERALL ARCHITECTURE 20 3.3 OPERATION PRINCIPLE 24 3.4 IMPLEMENTATION OF LC VCO 33 3.5 ALTERNATIVE DESIGN CHOICE OF LC PLL FOR DDR5 CLOCK BUFFER 35 CHAPTER 4 SIMULATION RESULT 37 4.1 PLL 37 4.2 LC VCO 42 CHAPTER 5 CONCLUSION 46 BIBLIOGRAPHY 47 초 록 49석