Temperature insensitive current reference circuit using standard CMOS devices

Abstract-In this paper, temperature insensitive current reference circuit is proposed. The reference current value is determined by using the threshold voltage controlled circuit. The main difference from the previous work[1] is that the circuit can be fabricated by the standard CMOS process. The resistor and the transistor physical parameter temperature dependences are compensated with each other to determine the output reference current. The detail temperature performance is analyzed, and is evaluated by simulations

Ultra Low Power Amplification and Digitization System for Neural Signal Recording Applications

The scope is to develop a tunable low power fully integrated bandpass filter and a low power second order sigma-delta ADC modulator for implantable neural signal amplification and digitization applications, with subthreshold circuit design techniques in different CMOS processes. Since biopotentials usually contain low frequency components, the neural filters in this project have to be able to achieve large and predictable time constant for implantable applications. Voltage biased pseudo-resistors are vulnerable to process variations and circuit imperfections, and hence not suitable for implantable applications. A current biased pseudo-resistor is implemented in the neural filters in this work to set the cutoff frequency, and a Taylor series is used to study its linearity. The filters with proposed current biased pseudo-resistors were fabricated in two different CMOS processes and tested. The test results verify that the filters with current biased pseudo-resistors are tunable, and not vulnerable to process variations and circuit imperfections. The filters with current biased pseudo-resistors meet the design requirements of fully integrated, implantable applications. The sigma-delta ADC modulator was designed and simulated in a half micron SOS CMOS process. The simulation results of the ADC confirm the possibility of an ultra low power ADC for neural signal recording applications.School of Electrical & Computer Engineerin

Design, Layout, and Testing of a Silicon Carbide-based Under Voltage Lock-out Circuit

Silicon carbide-based power devices play an increasingly important role in modern power conversion systems. Finding a means to reduce the size and complexity of these systems by even incremental amounts can have a significant impact on cost and reliability. One approach to achieving this goal is the die-level integration of gate driver circuitry with the SiC power devices. Aside from cost reductions, there are significant advantages to the integration of the gate driver circuits with the power devices. By integrating the gate driver circuitry with the power devices, the parasitic inductances traditionally seen between the gate driver and the switching devices can be significantly reduced, allowing faster switching speeds, which in turn leads to higher efficiencies, less aggressive thermal management requirements, and physically smaller passives. Collaborators from Toyota, Cree, the University of Arkansas, Oak Ridge National Labs, and Arkansas Power Electronics International have designed, fabricated, and tested a custom gate driver circuit implemented in a low-voltage SiC-based process by Cree. This gate driver implementation is the first step toward the goal of a completely integrated system. One key sub-component of this gate driver is the Under Voltage Lock-Out (UVLO) circuit, which asserts a signal whenever the supply voltage to the die falls below a set threshold and allows circuitry both on- and off-chip to take steps to prevent damage to the system. The work presented herein is the design, layout, and testing of a UVLO circuit implemented in the low-voltage silicon carbide process available from Cree. The UVLO was demonstrated to operate over a temperature range between -55 oC and 300 oC. An overview of the gate driver design, the fabrication process, and the trade-offs made during the UVLO circuit design process will be presented, as well as the integrated circuit layout workflow. A synopsis of the die testing apparatus and results will also be provided

Realization of Integrable Low- Voltage Companding Filters for Portable System Applications

Undoubtedly, today’s integrated electronic systems owe their remarkable performance primarily to the rapid advancements of digital technology since 1970s. The various important advantages of digital circuits are: its abstraction from the physical details of the actual circuit implementation, its comparative insensitiveness to variations in the manufacturing process, and the operating conditions besides allowing functional complexity that would not be possible using analog technology. As a result, digital circuits usually offer a more robust behaviour than their analog counterparts, though often with area, power and speed drawbacks. Due to these and other benefits, analog functionality has increasingly been replaced by digital implementations. In spite of the advantages discussed above, analog components are far from obsolete and continue to be key components of modern electronic systems. There is a definite trend toward persistent and ubiquitous use of analog electronic circuits in day-to-day life. Portable electronic gadgets, wireless communications and the widespread application of RF tags are just a few examples of contemporary developments. While all of these electronic systems are based on digital circuitry, they heavily rely on analog components as interfaces to the real world. In fact, many modern designs combine powerful digital systems and complementary analog components on a single chip for cost and reliability reasons. Unfortunately, the design of such systems-on-chip (SOC) suffers from the vastly different design styles of analog and digital components. While mature synthesis tools are readily available for digital designs, there is hardly any such support for analog designers apart from wellestablished PSPICE-like circuit simulators. Consequently, though the analog part usually occupies only a small fraction of the entire die area of an SOC, but its design often constitutes a major bottleneck within the entire development process. Integrated continuous-time active filters are the class of continuous-time or analog circuits which are used in various applications like channel selection in radios, anti-aliasing before sampling, and hearing aids etc. One of the figures of merit of a filter is the dynamic range; this is the ratio of the largest to the smallest signal that can be applied at the input of the filter while maintaining certain specified performance. The dynamic range required in the filter varies with the application and is decided by the variation in strength of the desired signal as well as that of unwanted signals that are to be rejected by the filter. It is well known that the power dissipation and the capacitor area of an integrated active filter increases in proportion to its dynamic range. This situation is incompatible with the needs of integrated systems, especially battery operated ones. In addition to this fundamental dependence of power dissipation on dynamic range, the design of integrated active filters is further complicated by the reduction of supply voltage of integrated circuits imposed by the scaling down of technologies to attain twin objective of higher speed and lower power consumption in digital circuits. The reduction in power consumption with decreasing supply voltage does not apply to analog circuits. In fact, considerable innovation is required with a reduced supply voltage even to avoid increasing power consumption for a given signal to noise ratio (S/N). These aspects pose a great hurdle to the active filter designer. A technique which has attracted the attention of circuit designers as a possible route to filters with higher dynamic range per unit power consumption is “companding”. Companding (compression-expansion) filters are a very promising subclass of continuous-time analog filters, where the input (linear) signal is initially compressed before it will be handled by the core (non-linear) system. In order to preserve the linear operation of the whole system, the non-linear signal produced by the core system is converted back to a linear output signal by employing an appropriate output stage. The required compression and expansion operations are performed by employing bipolar transistors in active region or MOS transistors in weak inversion; the systems thus derived are known as logarithmic-domain (logdomain) systems. In case MOS transistors operated in saturation region are employed, the derived structures are known as Square-root domain systems. Finally, the third class of companding filters can also be obtained by employing bipolar transistors in active region or MOS transistors in weak inversion; the derived systems are known as Sinh-domain systems. During the last several years, a significant research effort has been already carried out in the area of companding circuits. This is due to the fact that their main advantages are the capability for operation in low-voltage environment and large dynamic range originated from their companding nature, electronic tunability of the frequency characteristics, absence of resistors and the potential for operations in varied frequency regions.Thus, it is obvious that companding filters can be employed for implementing high-performance analog signal processing in diverse frequency ranges. For example, companding filters could be used for realizing subsystems in: xDSL modems, disk drive read channels, biomedical electronics, Bluetooth/ZigBee applications, phaselocked loops, FM stereo demodulator, touch-tone telephone tone decoder and crossover network used in a three-way high-fidelity loudspeaker etc. A number of design methods for companding filters and their building blocks have been introduced in the literature. Most of the proposed filter structures operate either above 1.5V or under symmetrical (1.5V) power supplies. According to data that provides information about the near future of semiconductor technology, International Technology Roadmap for Semiconductors (ITRS), in 2013, the supply voltage of digital circuits in 32 nm technology will be 0.5 V. Therefore, the trend for the implementation of analog integrated circuits is the usage of low-voltage building blocks that use a single 0.5-1.5V power supply. Therefore, the present investigation was primarily concerned with the study and design of low voltage and low power Companding filters. The work includes the study about: the building blocks required in implementing low voltage and low power Companding filters; the techniques used to realize low voltage and low power Companding filters and their various areas of application. Various novel low voltage and low power Companding filter designs have been developed and studied for their characteristics to be applied in a particular portable area of application. The developed designs include the N-th order universal Companding filter designs, which have been reported first time in the open literature. Further, an endeavor has been made to design Companding filters with orthogonal tuning of performance parameters so that the designs can be simultaneously used for various features. The salient features of each of the developed circuit are described. Electronic tunability is one of the major features of all of the designs. Use of grounded capacitors and resistorless designs in all the cases makes the designs suitable for IC technology. All the designs operate in a low-voltage and low-power environment essential for portable system applications. Unless specified otherwise, all the investigations on these designs are based on the PSPICE simulations using model parameters of the NR100N bipolar transistors and BSIM 0.35μm/TSMC 0.25μm /TSMC 0.18μm CMOS process MOS transistors. The performance of each circuit has been validated by comparing the characteristics obtained using simulation with the results present in the open literature. The proposed designs could not be realized in silicon due to non-availability of foundry facility at the place of study. An effort has already been started to realize some of the designs in silicon and check their applicability in practical circuits. At the basic level, one of the proposed Companding filter designs was implemented using the commercially available transistor array ICs (LM3046N) and was found to verify the theoretical predictions obtained from the simulation results

A 0.1 THD, 1 M ohm to 1 G Ohm Tunable, Temperature Compensated Transimpedance Amplifier Using a Multi Element Pseudo Resistor

In this paper, a transimpedance amplifier TIA is presented that utilizes a modified pseudo resistor PR with improved robustness against temperature and process variations, enhanced linearity, and reduced parasitics. Using a biasing scheme named pseudo current mirror, the conventional dependence on absolute process parameters is reduced to a dependence on matching of alike devices. The linearity and noise performance as well as the immunity against process variations of the presented TIA are improved by the series connection of multiple PR elements. Moreover, it is shown how implementing the design in a silicon on insulator SOI technology reduces critical parasitics, which in turn enables the use of the multi element PR in highspeed, high gain, and low distortion TIAs. A prototype realization in a 180 nm CMOS SOI technology achieves a tunability in transimpedance of three orders of magnitude from 1 G down to 1 M with corresponding bandwidths from 8 kHz to 2 MHz. By design, the contribution of shot noise is rendered negligible and the white noise floor of the prototype realization approaches the theoretical thermal noise limit, e.g., 5.5 fA Hz for a transimpedance of 1 G and 140 fA Hz for 1 M . Total harmonic distortion values of less than 0.1 are achieved for an input amplitude of 300 pAp p for 1 G , 4.0 nAp p for 100 M , and 40 nAp p for 10 M , and less than 1 is achieved for an input amplitude of 550 nAp p for 1 M . The presented TIA consumes an area of 0.07 mm2 and dissipates a power of 9.3 mW for the opamp and a maximum power of 0.2 mW for the PR from a 1.8 V suppl

Imaging Probe for Charged Particle Detection

Single Photon Avalanche Diodes (SPADs) are semiconductor devices that detect individual photons. However, they can also experience dark count rate (DCR), generating avalanche current even when no photons are present, which limits their ability to detect low-level signals. SPADs characterization is important to gain insight into their behavior and improve their performance for various applications. This thesis discusses the development of a portable detection probe that uses the APIX2LF chip, which contains arrays of SPADs that were produced using a 150 nm standard CMOS process. A prototype board, that includes a battery, front-end electronics, and a microcontroller acting as the interface between the sensor and the PC was developed and tested using a beta-emitting source. Additionally, custom firmware was designed for the microcontroller and an automatic data acquisition framework was developed for the characterization of the DCR of six APIX2LF chips at different bias voltages and temperatures.This thesis discusses the development of a portable detection probe that uses the APIX2LF chip, which contains arrays of SPADs that were produced using a 150 nm standard CMOS process. A prototype board, that includes a battery, front-end electronics, and a microcontroller acting as the interface between the sensor and the PC was developed and tested using a beta-emitting source. Additionally, custom firmware was designed for the microcontroller and an automatic data acquisition framework was developed for the characterization of the DCR of six APIX2LF chips at different bias voltages and temperatures

Chemical Bionics - a novel design approach using ion sensitive field effect transistors

In the late 1980s Carver Mead introduced Neuromorphic engineering in which various aspects of the neural systems of the body were modelled using VLSI1 circuits. As a result most bio-inspired systems to date concentrate on modelling the electrical behaviour of neural systems such as the eyes, ears and brain. The reality is however that biological systems rely on chemical as well as electrical principles in order to function. This thesis introduces chemical bionics in which the chemically-dependent physiology of specific cells in the body is implemented for the development of novel bio-inspired therapeutic devices. The glucose dependent pancreatic beta cell is shown to be one such cell, that is designed and fabricated to form the first silicon metabolic cell. By replicating the bursting behaviour of biological beta cells, which respond to changes in blood glucose, a bio-inspired prosthetic for glucose homeostasis of Type I diabetes is demonstrated. To compliment this, research to further develop the Ion Sensitive Field Effect Transistor (ISFET) on unmodified CMOS is also presented for use as a monolithic sensor for chemical bionic systems. Problems arising by using the native passivation of CMOS as a sensing surface are described and methods of compensation are presented. A model for the operation of the device in weak inversion is also proposed for exploitation of its physical primitives to make novel monolithic solutions. Functional implementations in various technologies is also detailed to allow future implementations chemical bionic circuits. Finally the ISFET integrate and fire neuron, which is the first of its kind, is presented to be used as a chemical based building block for many existing neuromorphic circuits. As an example of this a chemical imager is described for spatio-temporal monitoring of chemical species and an acid base discriminator for monitoring changes in concentration around a fixed threshold is also proposed

Impedance matching and DC-DC converter designs for tunable radio frequency based mobile telecommunication systems

Tunability and adaptability for radio frequency (RF) front-ends are highly desirable because they not only enhance functionality and performance but also reduce the circuit size and cost. This thesis presents a number of novel design strategies in DC-DC converters, impedance networks and adaptive algorithms for tunable and adaptable RF based mobile telecommunication systems. Specifically, the studies are divided into three major directions: (a) high voltage switch controller based DC-DC converters for RF switch actuation; (b) impedance network designs for impedance transformation of RF switches; and (c) adaptive algorithms for determining the required impedance states at the RF switches. In the first stage, two-phase step-up switched-capacitor (SC) DC-DC converters are explored. The SC converter has a simple control method and a reduced physical volume. The research investigations started with the linear and the non-linear voltage gain topologies. The non-linear voltage gain topology provides a higher voltage gain in a smaller number of stages compared to the linear voltage gain topology. Amongst the non-linear voltage gain topologies, a Fibonacci SC converter has been identified as having lower losses and a higher conversion ratio compared to other topologies. However, the implementation of a high voltage (HV) gain Fibonacci SC converter is complex due to the requirement of widely different gate voltages for the transistors in the Fibonacci converter. Gate driving strategies have been proposed that only require a few auxiliary transistors in order to provide the required boosted voltages for switching the transistors on and off. This technique reduces the design complexity and increases the reliability of the HV Fibonacci SC converter. For the linear voltage gain topology, a high performance complementary-metaloxide- semiconductor (CMOS) based SC DC-DC converter has been proposed in this work. The HV SC DC-DC converter has been designed in low voltage (LV) transistors technology in order to achieve higher voltage gain. Adaptive biasing circuits have been proposed to eliminate the leakage current, hence avoiding latch-up which normally occurs with low voltage transistors when they are used in a high voltage design. Thus, the SC DC-DC converter achieves more than 25% higher boosted voltage compared to converters that use HV transistors. The proposed design provides a 40% power reduction through the charge recycling circuit that reduces the effect of non-ideality in integrated HV capacitors. Moreover, the SC DC-DC converter achieves a 45% smaller area than the conventional converter through optimising the design parameters. In the second stage, the impedance network designs for transforming the impedance of RF switches to the maximum achievable impedance tuning region are investigated. The maximum achievable tuning region is bounded by the fundamental properties of the selected impedance network topology and by the tunable values of the RF switches that are variable over a limited range. A novel design technique has been proposed in order to achieve the maximum impedance tuning region, through identifying the optimum electrical distance between the RF switches at the impedance network. By varying the electrical distance between the RF switches, high impedance tuning regions are achieved across multi frequency standards. This technique reduces the cost and the insertion loss of an impedance network as the required number of RF switches is reduced. The prototype demonstrates high impedance coverages at LTE (700MHz), GSM (900MHz) and GPS (1575MHz). Integration of a tunable impedance network with an antenna for frequency-agility at the RF front-end has also been discussed in this work. The integrated system enlarges the bandwidth of a patch antenna by four times the original bandwidth and also improves the antenna return loss. The prototype achieves frequency-agility from 700MHz to 3GHz. This work demonstrates that a single transceiver with multi frequency standards can be realised by using a tunable impedance network. In the final stage, improvement to an adaptive algorithm for determining the impedance states at the RF switches has been proposed. The work has resulted in one more novel design techniques which reduce the search time in the algorithm, thus minimising the risk of data loss during the impedance tuning process. The approach reduces the search time by more than an order of magnitude by exploiting the relationships among the mass spring’s coefficient values derived from the impedance network parameters, thereby significantly reducing the convergence time of the algorithm. The algorithm with the proposed technique converges in less than half of the computational time compared to the conventional approach, hence significantly improving the search time of the algorithm. The design strategies proposed in this work contribute towards the realisation of tunable and adaptable RF based mobile telecommunication systems

Application of Nonlinear Transistor Characteristics

This research presents three works all related by the subject of third-order distortion reduction in nonlinear circuits. Each one is a novel extension to previous work in that branch of electronics literature. All three follow the procedure of presenting a novel algebraic proof and following up with simulations and/or measurements to confirm the theoretical result. The works are generally themed around nonlinear low-frequency bipolar transistor circuits. Firstly, an investigation is conducted into a well documented effect in bipolar-junction transistors (BJTs) called inherent third-order distortion nulling. This effect is shown to be a fundamental result of the transistor’s transfer junction acting upon an input signal. The proof of a single BJT emitter-follower amplifier’s inherent null is examined which is well documented in the literature. This forms the basis for a novel extension in Darlington transistors where theory suggests the third-order null occurs at double the collector current of a single BJT. Discrete measurements of a CA3083 transistor array are undertaken and compared with theory and simulation data. These measurements confirm theory with reasonable accuracy. A temperature and process variation independent bias circuit is developed to solve one issue with using third-order distortion nulling. This work is interesting in that it branches into series resistance compensation for translinear circuits and stands as a useful circuit in its own right. Using stacks of matched forward-biased semiconductor junctions which conform to translinear conditions, a bias current can be generated which theoretically removes temperature and series resistance dependence on the particular BJT used. This proves useful for the previous work in distortion nulling, but also allows direct and accurate measurement of series resistance. Again, simulation and measurement data is obtained from discrete measurements of the proposed circuit, and the results conform with theory to a reasonable degree. Lastly, this work presents the analysis of a cascoded-compensation (Cascomp) amplifier. It presents the first fully nonlinear derivation of the Cascomp’s transfer function and its associated harmonic and intermodulation distortion components. The derivation reveals an interesting characteristic in which the third-order intermodulation distortion has multiple local minima. This characteristic has not yet been presented in the literature, and allows better optimisation of Cascomp amplifiers in any application. Again, this characteristic and its potential benefits are confirmed with simulation and discrete measurements. Observations of the presented works are discussed and built upon in the last chapter. This leads to suggestions on future research topics branching on from these works