Analysis and design of wideband voltage controlled oscillators using self-oscillating active inductors.

Voltage controlled oscillators (VCOs) are essential components of RF circuits used in transmitters and receivers as sources of carrier waves with variable frequencies. This, together with a rapid development of microelectronic circuits, led to an extensive research on integrated implementations of the oscillator circuits. One of the known approaches to oscillator design employs resonators with active inductors electronic circuits simulating the behavior of passive inductors using only transistors and capacitors. Such resonators occupy only a fraction of the silicon area necessary for a passive inductor, and thus allow to use chip area more eectively. The downsides of the active inductor approach include: power consumption and noise introduced by transistors. This thesis presents a new approach to active inductor oscillator design using selfoscillating active inductor circuits. The instability necessary to start oscillations is provided by the use of a passive RC network rather than a power consuming external circuit employed in the standard oscillator approach. As a result, total power consumption of the oscillator is improved. Although, some of the active inductors with RC circuits has been reported in the literature, there has been no attempt to utilise this technique in wideband voltage controlled oscillator design. For this reason, the dissertation presents a thorough investigation of self-oscillating active inductor circuits, providing a new set of design rules and related trade-os. This includes: a complete small signal model of the oscillator, sensitivity analysis, large signal behavior of the circuit and phase noise model. The presented theory is conrmed by extensive simulations of wideband CMOS VCO circuit for various temperatures and process variations. The obtained results prove that active inductor oscillator performance is obtained without the use of standard active compensation circuits. Finally, the concept of self-oscillating active inductor has been employed to simple and fast OOK (On-Off Keying) transmitter showing energy eciency comparable to the state of the art implementations reported in the literature

RF CMOS Oscillators for Modern Wireless Applications

While mobile phones enjoy the largest production volume ever of any consumer electronics products, the demands they place on radio-frequency (RF) transceivers are particularly aggressive, especially on integration with digital processors, low area, low power consumption, while being robust against process-voltage-temperature variations. Since mobile terminals inherently operate on batteries, their power budget is severely constrained. To keep up with the ever increasing data-rate, an ever-decreasing power per bit is required to maintain the battery lifetime. The RF oscillator is the second most power-hungry block of a wireless radio (after power amplifiers). Consequently, any power reduction in an RF oscillator will greatly benefit the overall power efficiency of the cellular transceiver. Moreover, the RF oscillators' purity limits the transceiver performance. The oscillator's phase noise results in power leakage into adjacent channels in a transmit mode and reciprocal mixing in a receive mode. On the other hand, the multi-standard and multi-band transceivers that are now trending demand wide tuning range oscillators. However, broadening the oscillator’s tuning range is usually at the expense of die area (cost) or phase noise. The main goal of this book is to bring forth the exciting and innovative RF oscillator structures that demonstrate better phase noise performance, lower cost, and higher power efficiency than currently achievable. Technical topics discussed in RF CMOS Oscillators for Modern Wireless Applications include: Design and analysis of low phase-noise class-F oscillators Analyze a technique to reduce 1/f noise up-conversion in the oscillators Design and analysis of low power/low voltage oscillators Wide tuning range oscillators Reliability study of RF oscillators in nanoscale CMO

캘리브레이션이 필요없는 위상고정 루프의 설계

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2017. 2. 김재하.A PVT-insensitive-bandwidth PLL and a chirp frequency synthesizer PLL are proposed using a constant-relative-gain digitally-controlled oscillator (DCO), a constant-gain time-to-digital converter (TDC), and a simple digital loop filter (DLF) without an explicit calibration or additional circuit components. A digital LC-PLL that realizes a PVT-insensitive loop bandwidth (BW) by using the constant-relative-gain LC-DCO and constant-gain TDC is proposed. In other words, based on ratiometric circuit designs, the LC-DCO can make a fixed percent change to its frequency for a unit change in its digital input and the TDC can maintain a fixed range and resolution measured in reference unit intervals (UIs) across PVT variations. With such LC-DCO and TDC, the proposed PLL can realize a bandwidth which is a constant fraction of the reference frequency even with a simple proportional-integral digital loop filter without any explicit calibration loops. The prototype digital LC-PLL fabricated in a 28-nm CMOS demonstrates a frequency range of 8.38~9.34 GHz and 652-fs,rms integrated jitter from 10-kHz to 1-GHz at 8.84-GHz while dissipating 15.2-mW and occupying 0.24-mm^2. Also, the PLL across three different die samples and supply voltage ranging from 1.0 to 1.2V demonstrates a nearly constant BW at 822-kHz with the variation of ±4.25-% only. A chirp frequency synthesizer PLL (FS-PLL) that is capable of precise triangular frequency modulation using type-III digital LC-PLL architecture for X-band FMCW imaging radar is proposed. By employing a phase-modulating two-point modulation (TPM), constant-gain TDC, and a simple second-order DLF with polarity-alternating frequency ramp estimator, the PLL achieves a gain self-tracking TPM realizing a frequency chirp with fast chirp slope (=chirp BW/chirp period) without increasing frequency errors around the turn-around points, degrading the effective resolution achievable. A prototype chirp FS-PLL fabricated in a 65nm CMOS demonstrates that the PLL can generate a precise triangular chirp profile centered at 8.9-GHz with 940-MHz bandwidth and 28.8-us period with only 1.9-MHz,rms frequency error including the turn-around points and 14.8-mW power dissipation. The achieved 32.63-MHz/us chirp slope is higher than that of FMCW FS-PLLs previously reported by 2.6x.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 5 CHAPTER 2 CONVENTIONAL PHASE-LOCKED LOOP 7 2.1 CHARGE-PUMP PLL 7 2.1.1 OPERATING PRINCIPLE 7 2.1.2 LOOP DYNAMICS 9 2.2 DIGITAL PLL 10 2.2.1 OPERATING PRINCIPLE 11 2.2.2 LOOP DYNAMICS 12 CHAPTER 3 VARIATIONS ON PHASE-LOCKED LOOP 14 3.1 OSCILLATOR GAIN VARIATION 14 3.1.1 RING VOLTAGE-CONTROLLED OSCILLATOR 15 3.1.2 LC VOLTAGE-CONTROLLED OSCILLATOR 17 3.1.3 LC DIGITALLY-CONTROLLED OSCILLATOR 19 3.2 PHASE DETECTOR GAIN VARIATION 20 3.2.1 LINEAR PHASE DETECTOR 20 3.2.2 LINEAR TIME-TO-DIGITAL CONVERTER 21 CHAPTER 4 PROPOSED DCO AND TDC FOR CALIBRATION-FREE PLL 23 4.1 DIGTALLY-CONTROLLED OSCILLATOR (DCO) 25 4.1.1 OVERVIEW 24 4.1.2 CONSTANT-RELATIVE-GAIN DCO 26 4.2 TIME-TO-DIGITAL CONVERTER (TDC) 28 4.2.1 OVERVIEW 28 4.2.2 CONSTANT-GAIN TDC 30 CHAPTER 5 PVT-INSENSITIVE-BANDWIDTH PLL 35 5.1 OVERVIEW 36 5.2 PRIOR WORKS 37 5.3 PROPOSED PVT-INSENSITIVE-BANDWIDTH PLL 39 5.4 CIRCUIT IMPLEMENTATION 41 5.4.1 CAPACITOR-TUNED LC-DCO 41 5.4.2 TRANSFORMER-TUNED LC-DCO 45 5.4.3 OVERSAMPLING-BASED CONSTANT-GAIN TDC 49 5.4.4 PHASE DIGITAL-TO-ANALOG CONVERTER 52 5.4.5 DIGITAL LOOP FILTER 54 5.4.6 FREQUENCY DIVIDER 55 5.4.7 BANG-BANG PHASE-FREQUENCY DETECTOR 56 5.5 CELL-BASED DESIGN FLOW 57 5.6 MEASUREMENT RESULTS 58 CHAPTER 6 CHIRP FREQUENCY SYNTHESIZER PLL 66 6.1 OVERVIEW 67 6.2 PRIOR WORKS 71 6.3 PROPOSED CHIRP FREQUENCY SYNTHESIZER PLL 75 6.4 CIRCUIT IMPLEMENTATION 83 6.4.1 SECOND-ORDER DIGITAL LOOP FILTER 83 6.4.2 PHASE MODULATOR 84 6.4.3 CONSTANT-GAIN TDC 85 6.4.4 VRACTOR-BASED LC-DCO 87 6.4.5 OVERALL CLOCK CHAIN 90 6.5 MEASUREMENT RESULTS 91 6.6 SIGNAL-TO-NOISE RATIO OF RADAR 98 CHAPTER 7 CONCLUSION 100 BIBLIOGRAPHY 102 초록 109Docto