Reconfigurable Receiver Front-Ends for Advanced Telecommunication Technologies

The exponential growth of converging technologies, including augmented reality, autonomous vehicles, machine-to-machine and machine-to-human interactions, biomedical and environmental sensory systems, and artificial intelligence, is driving the need for robust infrastructural systems capable of handling vast data volumes between end users and service providers. This demand has prompted a significant evolution in wireless communication, with 5G and subsequent generations requiring exponentially improved spectral and energy efficiency compared to their predecessors. Achieving this entails intricate strategies such as advanced digital modulations, broader channel bandwidths, complex spectrum sharing, and carrier aggregation scenarios. A particularly challenging aspect arises in the form of non-contiguous aggregation of up to six carrier components across the frequency range 1 (FR1). This necessitates receiver front-ends to effectively reject out-of-band (OOB) interferences while maintaining high-performance in-band (IB) operation. Reconfigurability becomes pivotal in such dynamic environments, where frequency resource allocation, signal strength, and interference levels continuously change. Software-defined radios (SDRs) and cognitive radios (CRs) emerge as solutions, with direct RF-sampling receivers offering a suitable architecture in which the frequency translation is entirely performed in digital domain to avoid analog mixing issues. Moreover, direct RF- sampling receivers facilitate spectrum observation, which is crucial to identify free zones, and detect interferences. Acoustic and distributed filters offer impressive dynamic range and sharp roll off characteristics, but their bulkiness and lack of electronic adjustment capabilities limit their practicality. Active filters, on the other hand, present opportunities for integration in advanced CMOS technology, addressing size constraints and providing versatile programmability. However, concerns about power consumption, noise generation, and linearity in active filters require careful consideration.This thesis primarily focuses on the design and implementation of a low-voltage, low-power RFFE tailored for direct sampling receivers in 5G FR1 applications. The RFFE consists of a balun low-noise amplifier (LNA), a Q-enhanced filter, and a programmable gain amplifier (PGA). The balun-LNA employs noise cancellation, current reuse, and gm boosting for wideband gain and input impedance matching. Leveraging FD-SOI technology allows for programmable gain and linearity via body biasing. The LNA's operational state ranges between high-performance and high-tolerance modes, which are apt for sensitivityand blocking tests, respectively. The Q-enhanced filter adopts noise-cancelling, current-reuse, and programmable Gm-cells to realize a fourth-order response using two resonators. The fourth-order filter response is achieved by subtracting the individual response of these resonators. Compared to cascaded and magnetically coupled fourth-order filters, this technique maintains the large dynamic range of second-order resonators. Fabricated in 22-nm FD-SOI technology, the RFFE achieves 1%-40% fractional bandwidth (FBW) adjustability from 1.7 GHz to 6.4 GHz, 4.6 dB noise figure (NF) and an OOB third-order intermodulation intercept point (IIP3) of 22 dBm. Furthermore, concerning the implementation uncertainties and potential variations of temperature and supply voltage, design margins have been considered and a hybrid calibration scheme is introduced. A combination of on-chip and off-chip calibration based on noise response is employed to effectively adjust the quality factors, Gm-cells, and resonance frequencies, ensuring desired bandpass response. To optimize and accelerate the calibration process, a reinforcement learning (RL) agent is used.Anticipating future trends, the concept of the Q-enhanced filter extends to a multiple-mode filter for 6G upper mid-band applications. Covering the frequency range from 8 to 20 GHz, this RFFE can be configured as a fourth-order dual-band filter, two bandpass filters (BPFs) with an OOB notch, or a BPF with an IB notch. In cognitive radios, the filter’s transmission zeros can be positioned with respect to the carrier frequencies of interfering signals to yield over 50 dB blocker rejection

Efficient and Interference-Resilient Wireless Connectivity for IoT Applications

With the coming of age of the Internet of Things (IoT), demand on ultra-low power (ULP) and low-cost radios will continue to boost tremendously. The Bluetooth-Low-energy (BLE) standard provides a low power solution to connect IoT nodes with mobile devices, however, the power of maintaining a connection with a reasonable latency remains the limiting factor in defining the lifetime of event-driven BLE devices. BLE radio power consumption is in the milliwatt range and can be duty cycled for average powers around 30μW, but at the expense of long latency. Furthermore, wireless transceivers traditionally perform local oscillator (LO) calibration using an external crystal oscillator (XTAL) that adds significant size and cost to a system. Removing the XTAL enables a true single-chip radio, but an alternate means for calibrating the LO is required. Innovations in both the system architecture and circuits implementation are essential for the design of truly ubiquitous receivers for IoT applications. This research presents two porotypes as back-channel BLE receivers, which have lower power consumption while still being robust in the presents of interference and able to receive back-channel message from BLE compliant transmitters. In addition, the first crystal-less transmitter with symmetric over-the-air clock recovery compliant with the BLE standard using a GFSK-Modulated BLE Packet is presented.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/162942/1/abdulalg_1.pd

Wearable electroencephalography for long-term monitoring and diagnostic purposes

Truly Wearable EEG (WEEG) can be considered as the future of ambulatory EEG units, which are the current standard for long-term EEG monitoring. Replacing these short lifetime, bulky units with long-lasting, miniature and wearable devices that can be easily worn by patients will result in more EEG data being collected for extended monitoring periods. This thesis presents three new fabricated systems, in the form of Application Specific Integrated Circuits (ASICs), to aid the diagnosis of epilepsy and sleep disorders by detecting specific clinically important EEG events on the sensor node, while discarding background activity. The power consumption of the WEEG monitoring device incorporating these systems can be reduced since the transmitter, which is the dominating element in terms of power consumption, will only become active based on the output of these systems. Candidate interictal activity is identified by the developed analog-based interictal spike selection system-on-chip (SoC), using an approximation of the Continuous Wavelet Transform (CWT), as a bandpass filter, and thresholding. The spike selection SoC is fabricated in a 0.35 μm CMOS process and consumes 950 nW. Experimental results reveal that the SoC is able to identify 87% of interictal spikes correctly while only transmitting 45% of the data. Sections of EEG data containing likely ictal activity are detected by an analog seizure selection SoC using the low complexity line length feature. This SoC is fabricated in a 0.18 μm CMOS technology and consumes 1.14 μW. Based on experimental results, the fabricated SoC is able to correctly detect 83% of seizure episodes while transmitting 52% of the overall EEG data. A single-channel analog-based sleep spindle detection SoC is developed to aid the diagnosis of sleep disorders by detecting sleep spindles, which are characteristic events of sleep. The system identifies spindle events by monitoring abrupt changes in the input EEG. An approximation of the median frequency calculation, incorporated as part of the system, allows for non-spindle activity incorrectly identified by the system as sleep spindles to be discarded. The sleep spindle detection SoC is fabricated in a 0.18 μm CMOS technology, consuming only 515 nW. The SoC achieves a sensitivity and specificity of 71.5% and 98% respectively.Open Acces

Nonlinear models and algorithms for RF systems digital calibration

Focusing on the receiving side of a communication system, the current trend in pushing the digital domain ever more closer to the antenna sets heavy constraints on the accuracy and linearity of the analog front-end and the conversion devices. Moreover, mixed-signal implementations of Systems-on-Chip using nanoscale CMOS processes result in an overall poorer analog performance and a reduced yield. To cope with the impairments of the low performance analog section in this "dirty RF" scenario, two solutions exist: designing more complex analog processing architectures or to identify the errors and correct them in the digital domain using DSP algorithms. In the latter, constraints in the analog circuits' precision can be offloaded to a digital signal processor. This thesis aims at the development of a methodology for the analysis, the modeling and the compensation of the analog impairments arising in different stages of a receiving chain using digital calibration techniques. Both single and multiple channel architectures are addressed exploiting the capability of the calibration algorithm to homogenize all the channels' responses of a multi-channel system in addition to the compensation of nonlinearities in each response. The systems targeted for the application of digital post compensation are a pipeline ADC, a digital-IF sub-sampling receiver and a 4-channel TI-ADC. The research focuses on post distortion methods using nonlinear dynamic models to approximate the post-inverse of the nonlinear system and to correct the distortions arising from static and dynamic errors. Volterra model is used due to its general approximation capabilities for the compensation of nonlinear systems with memory. Digital calibration is applied to a Sample and Hold and to a pipeline ADC simulated in the 45nm process, demonstrating high linearity improvement even with incomplete settling errors enabling the use of faster clock speeds. An extended model based on the baseband Volterra series is proposed and applied to the compensation of a digital-IF sub-sampling receiver. This architecture envisages frequency selectivity carried out at IF by an active band-pass CMOS filter causing in-band and out-of-band nonlinear distortions. The improved performance of the proposed model is demonstrated with circuital simulations of a 10th-order band pass filter, realized using a five-stage Gm-C Biquad cascade, and validated using out-of-sample sinusoidal and QAM signals. The same technique is extended to an array receiver with mismatched channels' responses showing that digital calibration can compensate the loss of directivity and enhance the overall system SFDR. An iterative backward pruning is applied to the Volterra models showing that complexity can be reduced without impacting linearity, obtaining state-of-the-art accuracy/complexity performance. Calibration of Time-Interleaved ADCs, widely used in RF-to-digital wideband receivers, is carried out developing ad hoc models because the steep discontinuities generated by the imperfect canceling of aliasing would require a huge number of terms in a polynomial approximation. A closed-form solution is derived for a 4-channel TI-ADC affected by gain errors and timing skews solving the perfect reconstruction equations. A background calibration technique is presented based on cyclo-stationary filter banks architecture. Convergence speed and accuracy of the recursive algorithm are discussed and complexity reduction techniques are applied

Design of a Customized multipurpose nano-enabled implantable system for in-vivo theranostics

The first part of this paper reviews the current development and key issues on implantable multi-sensor devices for in vivo theranostics. Afterwards, the authors propose an innovative biomedical multisensory system for in vivo biomarker monitoring that could be suitable for customized theranostics applications. At this point, findings suggest that cross-cutting Key Enabling Technologies (KETs) could improve the overall performance of the system given that the convergence of technologies in nanotechnology, biotechnology, micro&nanoelectronics and advanced materials permit the development of new medical devices of small dimensions, using biocompatible materials, and embedding reliable and targeted biosensors, high speed data communication, and even energy autonomy. Therefore, this article deals with new research and market challenges of implantable sensor devices, from the point of view of the pervasive system, and time-to-market. The remote clinical monitoring approach introduced in this paper could be based on an array of biosensors to extract information from the patient. A key contribution of the authors is that the general architecture introduced in this paper would require minor modifications for the final customized bio-implantable medical device

Development and Experimental Analysis of Wireless High Accuracy Ultra-Wideband Localization Systems for Indoor Medical Applications

This dissertation addresses several interesting and relevant problems in the field of wireless technologies applied to medical applications and specifically problems related to ultra-wideband high accuracy localization for use in the operating room. This research is cross disciplinary in nature and fundamentally builds upon microwave engineering, software engineering, systems engineering, and biomedical engineering. A good portion of this work has been published in peer reviewed microwave engineering and biomedical engineering conferences and journals. Wireless technologies in medicine are discussed with focus on ultra-wideband positioning in orthopedic surgical navigation. Characterization of the operating room as a medium for ultra-wideband signal transmission helps define system design requirements. A discussion of the first generation positioning system provides a context for understanding the overall system architecture of the second generation ultra-wideband positioning system outlined in this dissertation. A system-level simulation framework provides a method for rapid prototyping of ultra-wideband positioning systems which takes into account all facets of the system (analog, digital, channel, experimental setup). This provides a robust framework for optimizing overall system design in realistic propagation environments. A practical approach is taken to outline the development of the second generation ultra-wideband positioning system which includes an integrated tag design and real-time dynamic tracking of multiple tags. The tag and receiver designs are outlined as well as receiver-side digital signal processing, system-level design support for multi-tag tracking, and potential error sources observed in dynamic experiments including phase center error, clock jitter and drift, and geometric position dilution of precision. An experimental analysis of the multi-tag positioning system provides insight into overall system performance including the main sources of error. A five base station experiment shows the potential of redundant base stations in improving overall dynamic accuracy. Finally, the system performance in low signal-to-noise ratio and non-line-of-sight environments is analyzed by focusing on receiver-side digitally-implemented ranging algorithms including leading-edge detection and peak detection. These technologies are aimed at use in next-generation medical systems with many applications including surgical navigation, wireless telemetry, medical asset tracking, and in vivo wireless sensors

Design and Implementation of an RF Front-End for Software Defined Radios

Software Defined Radios have brought a major reformation in the design standards for radios, in which a large portion of the functionality is implemented through pro­ grammable signal processing devices, giving the radio the ability to change its op­ erating parameters to accommodate new features and capabilities. A software radio approach reduces the content of radio frequency and other analog components of the traditional radios and emphasizes digital signal processing to enhance overall receiver flexibility. Field Programmable Gate Arrays (FPGA) are a suitable technology for the hardware platform as they offer the potential of hardware-like performance coupled with software-like programmability. Software defined radio is a very broad field, encompassing the design of various technologies all the way from the antenna to RF, IF, and baseband digital design. The RF section primarily consists of analog hardware modules. The IF and baseband sections are primarily digital. It is the general process of the radio to convert the incoming signal from RF to IF and then IF to baseband for better signal processing system. In this thesis, some of major building blocks of a Software defined radio are de­ signed and implemented using FPGAs. The design of a Digital front end, which provides the bridge between the baseband and analog RF portions of a wireless receiver, is synthesized. The Digital front end receiver consists of a digital down converter(DDC) which in turn comprises of a direct digital frequency synthesizer (DDFS), a phase accumulator and a low pass filter. The signal processing block of the DDFS is executed using Co-ordinate Rotation Digital Computer (CORDIC) iii Abstract algorithm. Cascaded-Integrator-Comb filters (CIC) are implemented for changing the sample rate of the incoming data. Application of a DDC includes software ra­ dios, multicarrier, multimode digital receivers, micro and pico cell systems,broadband data applications, instrumentation and test equipment and in-building wireless tele­ phony. Also, in this thesis, interfaces for connecting Texas Instruments high speed and high resolution Analog-to-Digital converters (ADC) and Digital-to-Analog converters (DAC) with Xilinx Virtex-5 FPGAs are also implemented and demonstrated

無線センサネットワークのための超低消費電力と高感度CMOS RF受信機に関する研究

Wireless sensor networks (WSN) have been applied in wide range of applications and proved the more and more important contribution in the modern life. In order to evaluate a WSN, many metrics are considered such as cost, latency, power or quality of service. However, since the sensor nodes are usually deployed in large physical areas and inaccessible locations, the battery change becomes impossible. In this scenario, the power consumption is the most important metric. In a sensor node, the RF receiver is one of the communication devices, which consume a vast majority of power. Therefore, this thesis studies ultra low power RF receivers for the long lifetime of the sensor nodes. Currently, the WSNs use various frequency bands. However, for low power target, the sub-GHz frequency bands are preferred. In this study, ultra-low power 315 MHz and 920 MHz receivers will be proposed for short-range applications and long-range applications of the WSNs respectively. To achieve ultra-low power target, the thesis considers some issues in architecture, circuit design and fabrication technology for suitable choices. After considering different receiver architectures, the RF detection receiver with the On-Off-Keying (OOK) modulation is chosen. Then the thesis proposes solutions to reduce power consumption and concurrently guarantee high sensitivity for the receivers so that they can communicate at adequate distances for both short and long-range applications. First, a 920 MHz OOK receiver is designed for the long-range WSN applications. Typically, the RF amplifiers and local oscillators consume the most of power of RF receivers. In the RF detection receivers, the local oscillators are eliminated, however, the power consumption of the RF amplifiers is still dominant. By reducing the RF gain or removing the RF amplifier, the power consumption of the receivers can be reduced drastically. However, in this case the sensitivity is very limited. In order to overcome the trade-off between power consumption and sensitivity, the switched bias is applied to the RF amplifiers to reduce their power consumption substantially while guaranteeing high RF gain before RF detection. As a result, the receiver consumes only 53 W at 0.6 V supply with -82 dBm sensitivity at 10 kbps data rate. Next, an OOK receiver operating at 315 MHz for the short-range WSN applications with low complexity is proposed. In this receiver, the RF amplifier is controlled to operate intermittently for power reduction. Furthermore, taking advantage of the low carrier frequency, a comparator is used to convert the RF signal to a rail-to-rail stream and then data is demodulated in the digital domain. Therefore, no envelope detector or baseband amplifiers is required. The architecture of the receiver is verified by using discrete RF modules and FPGAs before it is designed on CMOS technology. By simulation with the physical layout, the 315 MHz OOK receiver consumes 27.6 W at 200 kbps and achieves -76.4 dBm sensitivity. Finally, the Synchronized-OOK (S-OOK) modulation scheme is proposed and then an S-OOK receiver operating in the 315 MHz frequency is developed to reduce power consumption more deeply. The S-OOK signal contains not only data but also clock information. By generating a narrow window, the RF front-end is enabled to receive signal only in a short period, therefore, power consumption of the receiver is reduced further. In addition, thank to the clock information contained in the input signal, the data and corresponding clock are demodulated simultaneously without a clock and data recovery circuit. The architecture of the S-OOK receiver is also verified by using discrete RF modules and FPGAs, then VLSI design is carried out. Physical layout simulation shows that the receiver can achieve -76.4 dBm sensitivity, consumes 8.39 W, 4.49 W, 1.36 W at 100 kbps, 50 kbps and 10 kbps respectively. In conclusion, with the objective is to look for solutions to minimize power consumption of receivers for extending the lifetime of sensor nodes while guaranteeing high sensitivity, this study proposed novel receiver architectures, which help reduce power consumption significantly. If using the coin battery CR2032 for power supply, the 920 MHz OOK receiver can work continuously in 1.45 years with communication distance of 259 meters; the 315 MHz OOK receivers can work continuously in 2.8 years with approximately 19 meters communication distance in free space. Whereas, the 315 MHz S-OOK receiver with the minimum power consumption of 1.36 W is suitable for batteryless sensor nodes.電気通信大学201

Clock Generation Design for Continuous-Time Sigma-Delta Analog-To-Digital Converter in Communication Systems

Software defined radio, a highly digitized wireless receiver, has drawn huge attention in modern communication system because it can not only benefit from the advanced technologies but also exploit large digital calibration of digital signal processing (DSP) to optimize the performance of receivers. Continuous-time (CT) bandpass sigma-delta (ΣΔ) modulator, used as an RF-to-digital converter, has been regarded as a potential solution for software defined ratio. The demand to support multiple standards motivates the development of a broadband CT bandpass ΣΔ which can cover the most commercial spectrum of 1GHz to 4GHz in a modern communication system. Clock generation, a major building block in radio frequency (RF) integrated circuits (ICs), usually uses a phase-locked loop (PLL) to provide the required clock frequency to modulate/demodulate the informative signals. This work explores the design of clock generation in RF ICs. First, a 2-16 GHz frequency synthesizer is proposed to provide the sampling clocks for a programmable continuous-time bandpass sigma-delta (ΣΔ) modulator in a software radio receiver system. In the frequency synthesizer, a single-sideband mixer combines feed-forward and regenerative mixing techniques to achieve the wide frequency range. Furthermore, to optimize the excess loop delay in the wideband system, a phase-tunable clock distribution network and a clock-controlled quantizer are proposed. Also, the false locking of regenerative mixing is solved by controlling the self-oscillation frequency of the CML divider. The proposed frequency synthesizer performs excellent jitter performance and efficient power consumption. Phase noise and quadrature phase accuracy are the common tradeoff in a quadrature voltage-controlled oscillator. A larger coupling ratio is preferred to obtain good phase accuracy but suffer phase noise performance. To address these fundamental trade-offs, a phasor-based analysis is used to explain bi-modal oscillation and compute the quadrature phase errors given by inevitable mismatches of components. Also, the ISF is used to estimate the noise contribution of each major noise source. A CSD QVCO is first proposed to eliminate the undesired bi-modal oscillation and enhance the quadrature phase accuracy. The second work presents a DCC QVCO. The sophisticated dynamic current-clipping coupling network reduces injecting noise into LC tank at most vulnerable timings (zero crossing points). Hence, it allows the use of strong coupling ratio to minimize the quadrature phase sensitivity to mismatches without degrading the phase noise performance. The proposed DCC QVCO is implemented in a 130-nm CMOS technology. The measured phase noise is -121 dBc/Hz at 1MHz offset from a 5GHz carrier. The QVCO consumes 4.2mW with a 1-V power supply, resulting in an outstanding Figure of Merit (FoM) of 189 dBc/Hz. Frequency divider is one of the most power hungry building blocks in a PLL-based frequency synthesizer. The complementary injection-locked frequency divider is proposed to be a low-power solution. With the complimentary injection schemes, the dividers can realize both even and odd division modulus, performing a more than 100% locking range to overcome the PVT variation. The proposed dividers feature excellent phase noise. They can be used for multiple-phase generation, programmable phase-switching frequency dividers, and phase-skewing circuits