560 research outputs found
Optical interconnection networks based on microring resonators
Optical microring resonators can be integrated on a chip to perform switching operations directly in the optical domain. Thus they become a building block to create switching elements in on-chip optical interconnection networks, which promise to overcome some of the limitations of current electronic networks. However, the peculiar asymmetric power losses of microring resonators impose new constraints on the design and control of on-chip optical networks. In this work, we study the design of multistage interconnection networks optimized for a particular metric that we name the degradation index, which characterizes the asymmetric behavior of microrings. We also propose a routing control algorithm to maximize the overall throughput, considering the maximum allowed degradation index as a constrain
On the scalability of feedback-based two-stage switch
The feedback-based two-stage switch does not require a central scheduler and can provide close to 100% throughput [3]. But the number of crosspoints required for the two stages of switch fabric is 2N2, and the average packet delay performance (even under light traffic load) is on the order of O(N) slots, where N is the switch size. To improve the performance of feedback-based two-stage switch when N is large, we adopt the Clos network for constructing a large switch from a set of smaller feedback-based switch modules. We call it a Clos-feedback switch. The potential problem of packet mis-sequencing is solved by using application-flow based load balancing. With recursive decomposition, a Clos network can degenerate into a Benes network. We show that for a Clos-feedback switch, the number of crosspoints required is reduced to 4N(2 log2N-1) and the average packet delay is cut down to O(log 2 N) slots. © 2012 IEEE.published_or_final_versio
On chip interconnects for multiprocessor turbo decoding architectures
International audienc
Scalability of Optical Interconnects Based on Microring Resonators
This letter investigates the use of optical microring resonators as switching elements (SEs) in large optical interconnection fabrics. We introduce a simple physical-layer model to assess scalability in crossbar- and Benes-based architectures.We also propose a new dilated SE that improves scalability to build fabrics of several terabits per second of aggregate capacit
Succinct Representations of Permutations and Functions
We investigate the problem of succinctly representing an arbitrary
permutation, \pi, on {0,...,n-1} so that \pi^k(i) can be computed quickly for
any i and any (positive or negative) integer power k. A representation taking
(1+\epsilon) n lg n + O(1) bits suffices to compute arbitrary powers in
constant time, for any positive constant \epsilon <= 1. A representation taking
the optimal \ceil{\lg n!} + o(n) bits can be used to compute arbitrary powers
in O(lg n / lg lg n) time.
We then consider the more general problem of succinctly representing an
arbitrary function, f: [n] \rightarrow [n] so that f^k(i) can be computed
quickly for any i and any integer power k. We give a representation that takes
(1+\epsilon) n lg n + O(1) bits, for any positive constant \epsilon <= 1, and
computes arbitrary positive powers in constant time. It can also be used to
compute f^k(i), for any negative integer k, in optimal O(1+|f^k(i)|) time.
We place emphasis on the redundancy, or the space beyond the
information-theoretic lower bound that the data structure uses in order to
support operations efficiently. A number of lower bounds have recently been
shown on the redundancy of data structures. These lower bounds confirm the
space-time optimality of some of our solutions. Furthermore, the redundancy of
one of our structures "surpasses" a recent lower bound by Golynski [Golynski,
SODA 2009], thus demonstrating the limitations of this lower bound.Comment: Preliminary versions of these results have appeared in the
Proceedings of ICALP 2003 and 2004. However, all results in this version are
improved over the earlier conference versio
Fast and scalable optical packet switch architecture for computer communication networks
We present a novel low latency, high throughput and scalable optical packet switch (UPS) capable to optically interconnect hundreds of input/output ports. We focus on a strictly non-blocking Spanke architecture with contention resolution based on wavelength conversion. Highly distributed control of the UPS reduces the switching time to few nanoseconds regardless the amount of inputs/outputs. Queuing node analysis (mean values analysis) of input buffers in a computer communication network with windowflow control confirms that the new architecture, unlike rearrangeable nonblocking (i.e. Benes) architecture, can operate with low latency and high throughput with a very large amount of input/output ports
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Lowest common ancestor interconnection networks
Lowest Common Ancestor (LCA) networks are built using switches capable of connecting u + d inputs/outputs in a permutation pattern. For n source nodes and I stages of switches, n/d switches are used in stage l - n/d - u/d in stage l - 2, and in general , n-u^l-i-l/d^l-i switches in stage i. The resulting hierarchical structure possesses interesting connectivity and permutational properties. A full characterization of LCA networks is presented together with a permutation routing algorithm for a family of LCA networks. The algorithm uses the network itself to collect and disseminate information about the permutation. A schedule of O(dp log_d/u n) passes is obtained with a switch set-up cost factor of O(log_d/u n) (p is the minimum number of passes that an algorithm with global knowledge schedules)
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