mRUBiS: An Exemplar for Model-Based Architectural Self-Healing and Self-Optimization

Self-adaptive software systems are often structured into an adaptation engine that manages an adaptable software by operating on a runtime model that represents the architecture of the software (model-based architectural self-adaptation). Despite the popularity of such approaches, existing exemplars provide application programming interfaces but no runtime model to develop adaptation engines. Consequently, there does not exist any exemplar that supports developing, evaluating, and comparing model-based self-adaptation off the shelf. Therefore, we present mRUBiS, an extensible exemplar for model-based architectural self-healing and self-optimization. mRUBiS simulates the adaptable software and therefore provides and maintains an architectural runtime model of the software, which can be directly used by adaptation engines to realize and perform self-adaptation. Particularly, mRUBiS supports injecting issues into the model, which should be handled by self-adaptation, and validating the model to assess the self-adaptation. Finally, mRUBiS allows developers to explore variants of adaptation engines (e.g., event-driven self-adaptation) and to evaluate the effectiveness, efficiency, and scalability of the engines

MORA - an architecture and programming model for a resource efficient coarse grained reconfigurable processor

This paper presents an architecture and implementation details for MORA, a novel coarse grained reconfigurable processor for accelerating media processing applications. The MORA architecture involves a 2-D array of several such processors, to deliver low cost, high throughput performance in media processing applications. A distinguishing feature of the MORA architecture is the co-design of hardware architecture and low-level programming language throughout the design cycle. The implementation details for the single MORA processor, and benchmark evaluation using a cycle accurate simulator are presented

HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems

Spin-Transfer Torque RAM (STT-RAM) is widely considered a promising alternative to SRAM in the memory hierarchy due to STT-RAM's non-volatility, low leakage power, high density, and fast read speed. The STT-RAM's small feature size is particularly desirable for the last-level cache (LLC), which typically consumes a large area of silicon die. However, long write latency and high write energy still remain challenges of implementing STT-RAMs in the CPU cache. An increasingly popular method for addressing this challenge involves trading off the non-volatility for reduced write speed and write energy by relaxing the STT-RAM's data retention time. However, in order to maximize energy saving potential, the cache configurations, including STT-RAM's retention time, must be dynamically adapted to executing applications' variable memory needs. In this paper, we propose a highly adaptable last level STT-RAM cache (HALLS) that allows the LLC configurations and retention time to be adapted to applications' runtime execution requirements. We also propose low-overhead runtime tuning algorithms to dynamically determine the best (lowest energy) cache configurations and retention times for executing applications. Compared to prior work, HALLS reduced the average energy consumption by 60.57% in a quad-core system, while introducing marginal latency overhead.Comment: To Appear on IEEE Transactions on Computers (TC

Reconfigurable interconnects in DSM systems: a focus on context switch behavior

Recent advances in the development of reconfigurable optical interconnect technologies allow for the fabrication of low cost and run-time adaptable interconnects in large distributed shared-memory (DSM) multiprocessor machines. This can allow the use of adaptable interconnection networks that alleviate the huge bottleneck present due to the gap between the processing speed and the memory access time over the network. In this paper we have studied the scheduling of tasks by the kernel of the operating system (OS) and its influence on communication between the processing nodes of the system, focusing on the traffic generated just after a context switch. We aim to use these results as a basis to propose a potential reconfiguration of the network that could provide a significant speedup

Design and Benchmark Testing for Open Architecture Reconfigurable Mobile Spirometer and Exhaled Breath Monitor with GPS and Data Telemetry.

Portable and wearable medical instruments are poised to play an increasingly important role in health monitoring. Mobile spirometers are available commercially, and are used to monitor patients with advanced lung disease. However, these commercial monitors have a fixed product architecture determined by the manufacturer, and researchers cannot easily experiment with new configurations or add additional novel sensors over time. Spirometry combined with exhaled breath metabolite monitoring has the potential to transform healthcare and improve clinical management strategies. This research provides an updated design and benchmark testing for a flexible, portable, open access architecture to measure lung function, using common Arduino/Android microcontroller technologies. To demonstrate the feasibility and the proof-of-concept of this easily-adaptable platform technology, we had 43 subjects (healthy, and those with lung diseases) perform three spirometry maneuvers using our reconfigurable device and an office-based commercial spirometer. We found that our system compared favorably with the traditional spirometer, with high accuracy and agreement for forced expiratory volume in 1 s (FEV1) and forced vital capacity (FVC), and gas measurements were feasible. This provides an adaptable/reconfigurable open access "personalized medicine" platform for researchers and patients, and new chemical sensors and other modular instrumentation can extend the flexibility of the device in the future