Design of high speed 1:4 demultiplexer for optical communication systems

Master'sMASTER OF ENGINEERIN

Inductorless CMOS Receiver Front-End Circuits for 10-Gb/s Optical Communications

[[abstract]]In this paper, a 10-Gb/s inductorless CMOS receiver front end is presented, including a transimpedance amplifier and a limiting amplifier. The transimpedance amplifier incorporates Regulated Cascode (RGC), active-inductor peaking, and intersecting active feedback circuits to achieve a transimpedance gain of 56 dB and a bandwidth of 8.27 GHz with a power dissipation of 35 mW. The limiting amplifier employs interleaving active feedback to achieve a differential voltage gain of 44.5 dB and a bandwidth of 10.3 GHz while consuming 226 mW. Both circuits are realized in 0.18- m CMOS technology with a 1.8-V supply.[[notice]]補正完畢[[incitationindex]]EI[[booktype]]紙

1.25 Gbit/s ITU-T G.984.2 burst-mode transimpedance amplifier without reset pins

A

A high speed serializer/deserializer design

A Serializer/Deserializer (SerDes) is a circuit that converts parallel data into a serial stream and vice versa. It helps solve clock/data skew problems, simplifies data transmission, lowers the power consumption and reduces the chip cost. The goal of this project was to solve the challenges in high speed SerDes design, which included the low jitter design, wide bandwidth design and low power design. A quarter-rate multiplexer/demultiplexer (MUX/DEMUX) was implemented. This quarter-rate structure decreases the required clock frequency from one half to one quarter of the data rate. It is shown that this significantly relaxes the design of the VCO at high speed and achieves lower power consumption. A novel multi-phase LC-ring oscillator was developed to supply a low noise clock to the SerDes. This proposed VCO combined an LC-tank with a ring structure to achieve both wide tuning range (11%) and low phase noise (-110dBc/Hz at 1MHz offset). With this structure, a data rate of 36 Gb/s was realized with a measured peak-to-peak jitter of 10ps using 0.18microm SiGe BiCMOS technology. The power consumption is 3.6W with 3.4V power supply voltage. At a 60 Gb/s data rate the simulated peak-to-peak jitter was 4.8ps using 65nm CMOS technology. The power consumption is 92mW with 2V power supply voltage. A time-to-digital (TDC) calibration circuit was designed to compensate for the phase mismatches among the multiple phases of the PLL clock using a three dimensional fully depleted silicon on insulator (3D FDSOI) CMOS process. The 3D process separated the analog PLL portion from the digital calibration portion into different tiers. This eliminated the noise coupling through the common substrate in the 2D process. Mismatches caused by the vertical tier-to-tier interconnections and the temperature influence in the 3D process were attenuated by the proposed calibration circuit. The design strategy and circuits developed from this dissertation provide significant benefit to both wired and wireless applications

A 2.5 GHz Optoelectronic Amplifier in 0.18 m CMOS

The ever-growing need for high speed data transmission is driven by multimedia and telecommunication demands. Traditional metallic media, such as copper coaxial cable, prove to be a limiting factor for high speed communications. Fiber optic methods provide a feasible solution that lacks the limitations of metallic mediums, including low bandwidth, cross talk caused by magnetic induction, and susceptibility to static and RF interferences. The first scientists to work with fibers optics started in 1970. One of the early challenges they faced was to produce glass fiber that was pure enough to be equal in performance with copper based media. Since then, the technology has advanced tremendously in terms of performance, quality, and consistency. The advancement of fiber optic communication has met its limits, not in the purity of its fiber media used to guide the data-modulated light wave, but in the conversion back and forth between electric signals to light. A high speed optic receiver must be used to convert the incident light into electrical signals. This thesis describes the design of a 2.5 GHz Optoelectronic Amplifier, the front end of an optic receiver. The discussion includes a survey of feasible topologies and an assessment of circuit techniques to enhance performance. The amplifier was designed and realized in a TSMC 0.18 µm CMOS process

Analysis and Design of Wideband CMOS Transimpedance Amplifiers Using Inductive Feedback

Optical receivers have an important role in high data rate wireline data communication systems. Nowadays, these receivers have data rates of multi Gb/s. To achieve such high data rate in the design of optical receivers, all the amplifiers in the signal path need to be wideband and at the same time have minimum gain variations in the passband. As a rule of thumb, the bandwidth of amplifiers in the optical receivers should be 70% of the data rate. The first component of the optical receiver is photodiode which converts photons received from optical fiber to current signals. The small current received from the photodiode is amplified using the transimpedance amplifier (TIA) which is one of the main building blocks in the receiver frontend. Due to high data rate of fiber optic communication systems the bandwidth of TIAs should be high and it should satisfy gain requirements. It has been shown that inductive feedback technique is capable of extending the bandwidth of CMOS TIAs amplifiers effectively. However, no mathematical analysis is available in the literature explaining this phenomenon. The main focus of this thesis is to explain mathematically the mechanism of bandwidth extension of CMOS TIAs with inductive feedback. In this thesis, it is shown mathematically that the bandwidth extension of inverter based CMOS TIAs with inductive feedback is due to either zero-pole cancellation or change in the characteristics of complex conjugate poles. It is shown that for large photodiode capacitance for example 150fF the phenomenon for the bandwidth extension is zero pole cancellation. In the case of small photodiode capacitance for example 50fF, the bandwidth extension happens due to change in the characteristics of complex conjugate poles. Finally, the zero pole cancellation using inductive feedback method for common source based transimpednace amplifier with resistive load using different values of photodiode capacitances has been analyzed. In addition to that a new 3-stage common source based transimpedance amplifier using inductive feedback technique is designed. The process of bandwidth extension is shown analytically and is confirmed with simulation results using well-known tools and technologies. To show the system level motivation, an eye diagram simulation is performed for all topologies and it is verified that bandwidth extension does not disturb the performance. Moreover, the concept is verified based on a frequency scaled down discrete implementation. In this thesis, for inverter based CMOS TIA using photodiode capacitances of 150fF and 50fF bandwidths of 16.7GHz and 29.7GHz are achieved. In the case of common source based TIAs, considering 50fF, 100fF, 150fF photodiode capacitances, -3dB bandwidths of 32.1GHz, 21.8GHz, and 15.8GHz are achieved. A new three-stage TIA is proposed which achieves bandwidths of 42.8GHz, 35.5GHz, and 28.5GHz for 50fF, 100fF, 150fF photodiode capacitances. Based on comparative analysis, it is shown that, inductive feedback is the most effective method to extend the bandwidth of TIAs in terms of number of inductors