345 research outputs found
Ultra-low Power Circuits for Internet of Things (IOT)
Miniaturized sensor nodes offer an unprecedented opportunity for the semiconductor industry which led to a rapid development of the application space: the Internet of Things (IoT). IoT is a global infrastructure that interconnects physical and virtual things which have the potential to dramatically improve people's daily lives. One of key aspect that makes IoT special is that the internet is expanding into places that has been ever reachable as device form factor continue to decreases. Extremely small sensors can be placed on plants, animals, humans, and geologic features, and connected to the Internet. Several challenges, however, exist that could possibly slow the development of IoT.
In this thesis, several circuit techniques as well as system level optimizations to meet the challenging power/energy requirement for the IoT design space are described. First, a fully-integrated temperature sensor for battery-operated, ultra-low power microsystems is presented. Sensor operation is based on temperature independent/dependent current sources that are used with oscillators and counters to generate a digital temperature code.
Second, an ultra-low power oscillator designed for wake-up timers in compact wireless sensors is presented. The proposed topology separates the continuous comparator from the oscillation path and activates it only for short period when it is required. As a result, both low power tracking and generation of precise wake-up signal is made possible.
Third, an 8-bit sub-ranging SAR ADC for biomedical applications is discussed that takes an advantage of signal characteristics. ADC uses a moving window and stores the previous MSBs voltage value on a series capacitor to achieve energy saving compared to a conventional approach while maintaining its accuracy.
Finally, an ultra-low power acoustic sensing and object recognition microsystem that uses frequency domain feature extraction and classification is presented. By introducing ultra-low 8-bit SAR-ADC with 50fF input capacitance, power consumption of the frontend amplifier has been reduced to single digit nW-level. Also, serialized discrete Fourier transform (DFT) feature extraction is proposed in a digital back-end, replacing a high-power/area-consuming conventional FFT.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/137157/1/seojeong_1.pd
Developing Next-generation Brain Sensing Technologies - A Review.
Advances in sensing technology raise the possibility of creating neural interfaces that can more effectively restore or repair neural function and reveal fundamental properties of neural information processing. To realize the potential of these bioelectronic devices, it is necessary to understand the capabilities of emerging technologies and identify the best strategies to translate these technologies into products and therapies that will improve the lives of patients with neurological and other disorders. Here we discuss emerging technologies for sensing brain activity, anticipated challenges for translation, and perspectives for how to best transition these technologies from academic research labs to useful products for neuroscience researchers and human patients
Ultra-low noise, high-frame rate readout design for a 3D-stacked CMOS image sensor
Due to the switch from CCD to CMOS technology, CMOS based image sensors have become
smaller, cheaper, faster, and have recently outclassed CCDs in terms of image quality. Apart
from the extensive set of applications requiring image sensors, the next technological
breakthrough in imaging would be to consolidate and completely shift the conventional CMOS
image sensor technology to the 3D-stacked technology. Stacking is recent and an innovative
technology in the imaging field, allowing multiple silicon tiers with different functions to be
stacked on top of each other. The technology allows for an extreme parallelism of the pixel
readout circuitry. Furthermore, the readout is placed underneath the pixel array on a 3D-stacked
image sensor, and the parallelism of the readout can remain constant at any spatial resolution of
the sensors, allowing extreme low noise and a high-frame rate (design) at virtually any sensor
array resolution.
The objective of this work is the design of ultra-low noise readout circuits meant for 3D-stacked
image sensors, structured with parallel readout circuitries. The readout circuit’s key
requirements are low noise, speed, low-area (for higher parallelism), and low power.
A CMOS imaging review is presented through a short historical background, followed by the
description of the motivation, the research goals, and the work contributions. The fundamentals
of CMOS image sensors are addressed, as a part of highlighting the typical image sensor features,
the essential building blocks, types of operation, as well as their physical characteristics and their
evaluation metrics. Following up on this, the document pays attention to the readout circuit’s
noise theory and the column converters theory, to identify possible pitfalls to obtain sub-electron
noise imagers. Lastly, the fabricated test CIS device performances are reported along with
conjectures and conclusions, ending this thesis with the 3D-stacked subject issues and the future
work. A part of the developed research work is located in the Appendices.Devido à mudança da tecnologia CCD para CMOS, os sensores de imagem em CMOS tornam se mais pequenos, mais baratos, mais rápidos, e mais recentemente, ultrapassaram os sensores
CCD no que respeita à qualidade de imagem. Para além do vasto conjunto de aplicações que
requerem sensores de imagem, o prĂłximo salto tecnolĂłgico no ramo dos sensores de imagem Ă©
o de mudar completamente da tecnologia de sensores de imagem CMOS convencional para a
tecnologia “3D-stacked”. O empilhamento de chips é relativamente recente e é uma tecnologia
inovadora no campo dos sensores de imagem, permitindo vários planos de silĂcio com diferentes
funções poderem ser empilhados uns sobre os outros. Esta tecnologia permite portanto, um
paralelismo extremo na leitura dos sinais vindos da matriz de pĂxeis. AlĂ©m disso, num sensor de
imagem de planos de silĂcio empilhados, os circuitos de leitura estĂŁo posicionados debaixo da
matriz de pĂxeis, sendo que dessa forma, o paralelismo pode manter-se constante para qualquer
resolução espacial, permitindo assim atingir um extremo baixo ruĂdo e um alto debito de
imagens, virtualmente para qualquer resolução desejada.
O objetivo deste trabalho Ă© o de desenhar circuitos de leitura de coluna de muito baixo ruĂdo,
planeados para serem empregues em sensores de imagem “3D-stacked” com estruturas
altamente paralelizadas. Os requisitos chave para os circuitos de leitura sĂŁo de baixo ruĂdo,
rapidez e pouca área utilizada, de forma a obter-se o melhor rácio.
Uma breve revisĂŁo histĂłrica dos sensores de imagem CMOS Ă© apresentada, seguida da
motivação, dos objetivos e das contribuições feitas. Os fundamentos dos sensores de imagem
CMOS sĂŁo tambĂ©m abordados para expor as suas caracterĂsticas, os blocos essenciais, os tipos
de operação, assim como as suas caracterĂsticas fĂsicas e suas mĂ©tricas de avaliação. No
seguimento disto, especial atenção Ă© dada Ă teoria subjacente ao ruĂdo inerente dos circuitos de
leitura e dos conversores de coluna, servindo para identificar os possĂveis aspetos que dificultem
atingir a tĂŁo desejada performance de muito baixo ruĂdo. Por fim, os resultados experimentais
do sensor desenvolvido sĂŁo apresentados junto com possĂveis conjeturas e respetivas conclusões,
terminando o documento com o assunto de empilhamento vertical de camadas de silĂcio, junto
com o possĂvel trabalho futuro
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