DDR5 클락 버퍼를 위한 LC PLL의 설계

학위논문(석사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022. 8. 정덕균.This thesis describes a wide-range, fast-locking LC PLL for DDR5 clock buffer application. To operate LC PLL at wide range of input frequency, proposed PLL uses LC VCO with 28GHz center frequency and calculates appropriate division ratio of programmable divider for certain input frequen-cy at transient state. Calculating division ratio is achieved by using integer counter and fractional counter, detecting frequency of input clock at transient state. After calculating division ratio, proposed PLL operates as 3rd order charge pump PLL with optimum current value to lock fast. Proposed PLL is described with Systemverilog and simulation results shows that proposed LC PLL operates at 1 ~ 4.2GHz input frequency, while successfully acquires to lock at under 1μs. Also, LC-VCO is designed in a 40nm CMOS and simulation results shows that tuning range of VCO is ±9.25% with respect to center frequency of 28.2GHz, and VCO dissipates 26.4mW and phase noise is –104.86dBc/Hz at 1MHz offset, operating at center fre-quency with 1.1V supply voltage.본 논문은 DDR5 Clock Buffer를 위한, 넓은 범위에서 빠르게 락을 하는 LC PLL에 대해서 설명한다. 넓은 범위의 입력 주파수에서 LC PLL을 동작하기 위해, 제안한 PLL은 28GHz가 중심 주파수인 LC VCO을 사용하여, 과도 상태에서 특정 입력 주파수에 알맞는 프로그램 가능한divider의 제수를 계산한다. 제수의 계산은 과도 상태에서 입력 클락의 주파수를 감지하는 정수 카운터와 소수 카운터를 통해 이루어진다. 제수의 계산 이후, 제안한 PLL은 빠르게 락을 하기 위한 최적의 전류 값으로 3차의 Charge pump PLL로 동작한다. 제안한 PLL은 systemverilog로 기술되었고 시뮬레이션 결과 제안한 LC PLL은 1 ~ 4.2GHz의 입력주파수에서 동작하며, 1us 이내에서 성공적으로 락을 한다. 또한, LC-VCO가 40nm CMOS 공정에서 설계되었고, 시뮬레이션 결과 VCO의 튜닝 범위가 중심 주파수 28.2GHz을 기준으로 ±9.25%이고, 중심 주파수와 1.1V 공급 전압에서 26.4mW의 전력을 소모하고, phase noise가 1MHz 오프셋에서 -104.86dBc/Hz임을 확인할 수 있었다.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 3 CHAPTER 2 BACKGROUND ON LC PLL 4 2.1 BASIS OF PLL 4 2.2 FREQUENCY RANGE AND LOCK TIME OF PLL 11 2.2.1 FREQUENCY RANGE 11 2.2.2 LOCK TIME 13 2.3 BASIS OF LC VCO 15 CHAPTER 3 DESIGN OF LC PLL FOR DDR5 CLOCK BUFFER 18 3.1 DESIGN CONSIDERATION 18 3.2 OVERALL ARCHITECTURE 20 3.3 OPERATION PRINCIPLE 24 3.4 IMPLEMENTATION OF LC VCO 33 3.5 ALTERNATIVE DESIGN CHOICE OF LC PLL FOR DDR5 CLOCK BUFFER 35 CHAPTER 4 SIMULATION RESULT 37 4.1 PLL 37 4.2 LC VCO 42 CHAPTER 5 CONCLUSION 46 BIBLIOGRAPHY 47 초 록 49석

캘리브레이션이 필요없는 위상고정 루프의 설계

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2017. 2. 김재하.A PVT-insensitive-bandwidth PLL and a chirp frequency synthesizer PLL are proposed using a constant-relative-gain digitally-controlled oscillator (DCO), a constant-gain time-to-digital converter (TDC), and a simple digital loop filter (DLF) without an explicit calibration or additional circuit components. A digital LC-PLL that realizes a PVT-insensitive loop bandwidth (BW) by using the constant-relative-gain LC-DCO and constant-gain TDC is proposed. In other words, based on ratiometric circuit designs, the LC-DCO can make a fixed percent change to its frequency for a unit change in its digital input and the TDC can maintain a fixed range and resolution measured in reference unit intervals (UIs) across PVT variations. With such LC-DCO and TDC, the proposed PLL can realize a bandwidth which is a constant fraction of the reference frequency even with a simple proportional-integral digital loop filter without any explicit calibration loops. The prototype digital LC-PLL fabricated in a 28-nm CMOS demonstrates a frequency range of 8.38~9.34 GHz and 652-fs,rms integrated jitter from 10-kHz to 1-GHz at 8.84-GHz while dissipating 15.2-mW and occupying 0.24-mm^2. Also, the PLL across three different die samples and supply voltage ranging from 1.0 to 1.2V demonstrates a nearly constant BW at 822-kHz with the variation of ±4.25-% only. A chirp frequency synthesizer PLL (FS-PLL) that is capable of precise triangular frequency modulation using type-III digital LC-PLL architecture for X-band FMCW imaging radar is proposed. By employing a phase-modulating two-point modulation (TPM), constant-gain TDC, and a simple second-order DLF with polarity-alternating frequency ramp estimator, the PLL achieves a gain self-tracking TPM realizing a frequency chirp with fast chirp slope (=chirp BW/chirp period) without increasing frequency errors around the turn-around points, degrading the effective resolution achievable. A prototype chirp FS-PLL fabricated in a 65nm CMOS demonstrates that the PLL can generate a precise triangular chirp profile centered at 8.9-GHz with 940-MHz bandwidth and 28.8-us period with only 1.9-MHz,rms frequency error including the turn-around points and 14.8-mW power dissipation. The achieved 32.63-MHz/us chirp slope is higher than that of FMCW FS-PLLs previously reported by 2.6x.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 5 CHAPTER 2 CONVENTIONAL PHASE-LOCKED LOOP 7 2.1 CHARGE-PUMP PLL 7 2.1.1 OPERATING PRINCIPLE 7 2.1.2 LOOP DYNAMICS 9 2.2 DIGITAL PLL 10 2.2.1 OPERATING PRINCIPLE 11 2.2.2 LOOP DYNAMICS 12 CHAPTER 3 VARIATIONS ON PHASE-LOCKED LOOP 14 3.1 OSCILLATOR GAIN VARIATION 14 3.1.1 RING VOLTAGE-CONTROLLED OSCILLATOR 15 3.1.2 LC VOLTAGE-CONTROLLED OSCILLATOR 17 3.1.3 LC DIGITALLY-CONTROLLED OSCILLATOR 19 3.2 PHASE DETECTOR GAIN VARIATION 20 3.2.1 LINEAR PHASE DETECTOR 20 3.2.2 LINEAR TIME-TO-DIGITAL CONVERTER 21 CHAPTER 4 PROPOSED DCO AND TDC FOR CALIBRATION-FREE PLL 23 4.1 DIGTALLY-CONTROLLED OSCILLATOR (DCO) 25 4.1.1 OVERVIEW 24 4.1.2 CONSTANT-RELATIVE-GAIN DCO 26 4.2 TIME-TO-DIGITAL CONVERTER (TDC) 28 4.2.1 OVERVIEW 28 4.2.2 CONSTANT-GAIN TDC 30 CHAPTER 5 PVT-INSENSITIVE-BANDWIDTH PLL 35 5.1 OVERVIEW 36 5.2 PRIOR WORKS 37 5.3 PROPOSED PVT-INSENSITIVE-BANDWIDTH PLL 39 5.4 CIRCUIT IMPLEMENTATION 41 5.4.1 CAPACITOR-TUNED LC-DCO 41 5.4.2 TRANSFORMER-TUNED LC-DCO 45 5.4.3 OVERSAMPLING-BASED CONSTANT-GAIN TDC 49 5.4.4 PHASE DIGITAL-TO-ANALOG CONVERTER 52 5.4.5 DIGITAL LOOP FILTER 54 5.4.6 FREQUENCY DIVIDER 55 5.4.7 BANG-BANG PHASE-FREQUENCY DETECTOR 56 5.5 CELL-BASED DESIGN FLOW 57 5.6 MEASUREMENT RESULTS 58 CHAPTER 6 CHIRP FREQUENCY SYNTHESIZER PLL 66 6.1 OVERVIEW 67 6.2 PRIOR WORKS 71 6.3 PROPOSED CHIRP FREQUENCY SYNTHESIZER PLL 75 6.4 CIRCUIT IMPLEMENTATION 83 6.4.1 SECOND-ORDER DIGITAL LOOP FILTER 83 6.4.2 PHASE MODULATOR 84 6.4.3 CONSTANT-GAIN TDC 85 6.4.4 VRACTOR-BASED LC-DCO 87 6.4.5 OVERALL CLOCK CHAIN 90 6.5 MEASUREMENT RESULTS 91 6.6 SIGNAL-TO-NOISE RATIO OF RADAR 98 CHAPTER 7 CONCLUSION 100 BIBLIOGRAPHY 102 초록 109Docto

Timing Signals and Radio Frequency Distribution Using Ethernet Networks for High Energy Physics Applications

Timing networks are used around the world in various applications from telecommunications systems to industrial processes, and from radio astronomy to high energy physics. Most timing networks are implemented using proprietary technologies at high operation and maintenance costs. This thesis presents a novel timing network capable of distributed timing with subnanosecond accuracy. The network, developed at CERN and codenamed “White- Rabbit”, uses a non-dedicated Ethernet link to distribute timing and data packets without infringing the sub-nanosecond timing accuracy required for high energy physics applications. The first part of this thesis proposes a new digital circuit capable of measuring time differences between two digital clock signals with sub-picosecond time resolution. The proposed digital circuit measures and compensates for the phase variations between the transmitted and received network clocks required to achieve the sub-nanosecond timing accuracy. Circuit design, implementation and performance verification are reported. The second part of this thesis investigates and proposes a new method to distribute radio frequency (RF) signals over Ethernet networks. The main goal of existing distributed RF schemes, such as Radio-Over-Fibre or Digitised Radio-Over-Fibre, is to increase the bandwidth capacity taking advantage of the higher performance of digital optical links. These schemes tend to employ dedicated and costly technologies, deemed unnecessary for applications with lower bandwidth requirements. This work proposes the distribution of RF signals over the “White-Rabbit” network, to convey phase and frequency information from a reference base node to a large numbers of remote nodes, thus achieving high performance and cost reduction of the timing network. Hence, this thesis reports the design and implementation of a new distributed RF system architecture; analysed and tested using a purpose-built simulation environment, with results used to optimise a new bespoke FPGA implementation. The performance is evaluated through phase-noise spectra, the Allan-Variance, and signalto- noise ratio measurements of the distributed signals

Hybrid NRZ/Multi-Tone Signaling for High-Speed Low-Power Wireline Transceivers

Over the past few decades, incessant growth of Internet networking traffic and High-Performance Computing (HPC) has led to a tremendous demand for data bandwidth. Digital communication technologies combined with advanced integrated circuit scaling trends have enabled the semiconductor and microelectronic industry to dramatically scale the bandwidth of high-loss interfaces such as Ethernet, backplane, and Digital Subscriber Line (DSL). The key to achieving higher bandwidth is to employ equalization technique to compensate the channel impairments such as Inter-Symbol Interference (ISI), crosstalk, and environmental noise. Therefore, todayâs advanced input/outputs (I/Os) has been equipped with sophisticated equalization techniques to push beyond the uncompensated bandwidth of the system. To this end, process scaling has continually increased the data processing capability and improved the I/O performance over the last 15 years. However, since the channel bandwidth has not scaled with the same pace, the required signal processing and equalization circuitry becomes more and more complicated. Thereby, the energy efficiency improvements are largely offset by the energy needed to compensate channel impairments. In this design paradigm, re-thinking about the design strategies in order to not only satisfy the bandwidth performance, but also to improve power-performance becomes an important necessity. It is well known in communication theory that coding and signaling schemes have the potential to provide superior performance over band-limited channels. However, the choice of the optimum data communication algorithm should be considered by accounting for the circuit level power-performance trade-offs. In this thesis we have investigated the application of new algorithm and signaling schemes in wireline communications, especially for communication between microprocessors, memories, and peripherals. A new hybrid NRZ/Multi-Tone (NRZ/MT) signaling method has been developed during the course of this research. The system-level and circuit-level analysis, design, and implementation of the proposed signaling method has been performed in the frame of this work, and the silicon measurement results have proved the efficiency and the robustness of the proposed signaling methodology for wireline interfaces. In the first part of this work, a 7.5 Gb/s hybrid NRZ/MT transceiver (TRX) for multi-drop bus (MDB) memory interfaces is designed and fabricated in 40 nm CMOS technology. Reducing the complexity of the equalization circuitry on the receiver (RX) side, the proposed architecture achieves 1 pJ/bit link efficiency for a MDB channel bearing 45 dB loss at 2.5 GHz. The measurement results of the first prototype confirm that NRZ/MT serial data TRX can offer an energy-efficient solution for MDB memory interfaces. Motivated by the satisfying results of the first prototype, in the second phase of this research we have exploited the properties of multi-tone signaling, especially orthogonality among different sub-bands, to reduce the effect of crosstalk in high-dense wireline interconnects. A four-channel transceiver has been implemented in a standard CMOS 40 nm technology in order to demonstrate the performance of NRZ/MT signaling in presence of high channel loss and strong crosstalk noise. The proposed system achieves 1 pJ/bit power efficiency, while communicating over a MDB memory channel at 36 Gb/s aggregate data rate

Digital enhancement techniques for fractional-N frequency synthesizers

Meeting the demand for unprecedented connectivity in the era of internet-of-things (IoT) requires extremely energy efficient operation of IoT nodes to extend battery life. Managing the data traffic generated by trillions of such nodes also puts severe energy constraints on the data centers. Clock generators that are essential elements in these systems consume significant power and therefore must be optimized for low power and high performance. The focus of this thesis is on improving the energy efficiency of frequency synthesizers and clocking modules by exploring design techniques at both the architectural and circuit levels. In the first part of this work, a digital fractional-N phase locked loop (FNPLL) that employs a high resolution time-to-digital converter (TDC) and a truly ΔΣ fractional divider to achieve low in-band noise with a wide bandwidth is presented. The fractional divider employs a digital-to-time converter (DTC) to cancel out ΔΣ quantization noise in time domain, thus alleviating TDC dynamic range requirements. The proposed digital architecture adopts a narrow range low-power time-amplifier based TDC (TA-TDC) to achieve sub 1ps resolution. Fabricated in 65nm CMOS process, the prototype PLL achieves better than -106dBc/Hz in-band noise and 3MHz PLL bandwidth at 4.5GHz output frequency using 50MHz reference. The PLL achieves excellent jitter performance of 490fsrms, while consumes only 3.7mW. This translates to the best reported jitter-power figure-of-merit (FoM) of -240.5dB among previously reported FNPLLs. Phase noise performance of ring oscillator based digital FNPLLs is severely compromised by conflicting bandwidth requirements to simultaneously suppress oscillator phase and quantization noise introduced by the TDC, ΔΣ fractional divider, and digital-to-analog converter (DAC). As a consequence, their FoM that quantifies the power-jitter tradeoff is at least 25dB worse than their LC-oscillator based FNPLL counterparts. In the second part of this thesis, we seek to close this performance gap by extending PLL bandwidth using quantization noise cancellation techniques and by employing a dual-path digital loop filter to suppress the detrimental impact of DAC quantization noise. A prototype was implemented in a 65nm CMOS process operating over a wide frequency range of 2.0GHz-5.5GHz using a modified extended range multi-modulus divider with seamless switching. The proposed digital FNPLL achieves 1.9psrms integrated jitter while consuming only 4mW at 5GHz output. The measured in-band phase noise is better than -96 dBc/Hz at 1MHz offset. The proposed FNPLL achieves wide bandwidth up to 6MHz using a 50 MHz reference and its FoM is -228.5dB, which is at about 20dB better than previously reported ring-based digital FNPLLs. In the third part, we propose a new multi-output clock generator architecture using open loop fractional dividers for system-on-chip (SoC) platforms. Modern multi-core processors use per core clocking, where each core runs at its own speed. The core frequency can be changed dynamically to optimize for performance or power dissipation using a dynamic frequency scaling (DFS) technique. Fast frequency switching is highly desirable as long as it does not interrupt code execution; therefore it requires smooth frequency transitions with no undershoots. The second main requirement in processor clocking is the capability of spread spectrum frequency modulation. By spreading the clock energy across a wide bandwidth, the electromagnetic interference (EMI) is dramatically reduced. A conventional PLL clock generation approach suffers from a slow frequency settling and limited spread spectrum modulation capabilities. The proposed open loop fractional divider architecture overcomes the bandwidth limitation in fractional-N PLLs. The fractional divider switches the output frequency instantaneously and provides an excellent spread spectrum performance, where precise and programmable modulation depth and frequency can be applied to satisfy different EMI requirements. The fractional divider has unlimited modulation bandwidth resulting in spread spectrum modulation with no filtering, unlike fractional-N PLL; consequently it achieves higher EMI reduction. A prototype fractional divider was implemented in a 65nm CMOS process, where the measured peak-to-peak jitter is less than 27ps over a wide frequency range from 20MHz to 1GHz. The total power consumption is about 3.2mW for 1GHz output frequency. The all-digital implementation of the divider occupies the smallest area of 0.017mm2 compared to state-of-the-art designs. As the data rate of serial links goes higher, the jitter requirements of the clock generator become more stringent. Improving the jitter performance of conventional PLLs to less than (200fsrms) always comes with a large power penalty (tens of mWs). This is due to the PLL coupled noise bandwidth trade-off, which imposes stringent noise requirements on the oscillator and/or loop components. Alternatively, an injection-locked clock multiplier (ILCM) provides many advantages in terms of phase noise, power, and area compared to classical PLLs, but they suffer from a narrow lock-in range and a high sensitivity to PVT variations especially at a large multiplication factor (N). In the fourth part of this thesis, a low-jitter, low-power LC-based ILCM with a digital frequency-tracking loop (FTL) is presented. The proposed FTL relies on a new pulse gating technique to continuously tune the oscillator's free-running frequency. The FTL ensures robust operation across PVT variations and resolves the race condition existing in injection locked PLLs by decoupling frequency tuning from the injection path. As a result, the phase locking condition is only determined by the injection path. This work also introduces an accurate theoretical large-signal analysis for phase domain response (PDR) of injection locked oscillators (ILOs). The proposed PDR analysis captures the asymmetric nature of ILO's lock-in range, and the impact of frequency error on injection strength and phase noise performance. The proposed architecture and analysis are demonstrated by a prototype fabricated in 65 nm CMOS process with active area of 0.25mm2. The prototype ILCM multiplies the reference frequency by 64 to generate an output clock in the range of 6.75GHz-8.25GHz. A superior jitter performance of 190fsrms is achieved, while consuming only 2.25mW power. This translates to a best FoM of -251dB. Unlike conventional PLLs, ILCMs have been fundamentally limited to only integer-N operation and cannot synthesize fractional-N frequencies. In the last part of this thesis, we extend the merits of ILCMs to fractional-N and overcome this fundamental limitation. We employ DTC-based QNC techniques in order to align injected pulses to the oscillator's zero crossings, which enables it to pull the oscillator toward phase lock, thus realizing a fractional-N ILCM. Fabricated in 65nm CMOS process, a prototype 20-bit fractional-N ILCM with an output range of 6.75GHz-8.25GHz consumes only 3.25mW. It achieves excellent jitter performance of 110fsrms and 175fsrms in integer- and fractional-N modes respectively, which translates to the best-reported FoM in both integer- (-255dB) and fractional-N (-252dB) modes. The proposed fractional-N ILCM also features the first-reported rapid on/off capability, where the transient absolute jitter performance at wake-up is bounded below 4ps after less than 4ns. This demonstrates almost instantaneous phase settling. This unique capability enables tremendous energy saving by turning on the clock multiplier only when needed. This energy proportional operation leverages idle times to save power at the system-level of wireline and wireless transceivers