-Memory Computing Based Reliable and High Speed Schmitt trigger 10T SRAM cell design

Static random access memories (SRAM) are useful building blocks in various applications, including cache memories, integrated data storage systems, and microprocessors. The von Neumann bottleneck difficulties are solved by in-memory computing. It eliminates unnecessary frequent data transfer between memory and processing units simultaneously. In this research, the replica-based 10T SRAM design for in-memory computing (IMC) is designed by adapting the word line control scheme in 14nm CMOS technology. In order to achieve high reading and writing capability, the Schmitt trigger inverter was used for energy-saving and stable use. To speed up the writing process of the design, a single transistor is inserted between the cross-coupled inverters. In addition, to increase the node capacity, the voltage boosting circuitry is emphasized. The adaptive word line control scheme was utilized by integrating the replica column based circuit. The Replica approach regulates signal flow through the core by using a dummy column and a dummy row in RAM. To demonstrate the viability of the suggested design, the simulated outcomes are contrasted with those of existing designs. The various performance metrics examined are Read Static Noise Margin (RSNM), Write (WSNM), Hold (HSNM), Read Access Delay (RAD), Write Access Delay (WAD), Read performance and Write performance the varying supply voltage is evaluated

Modeling and experimental verification of single event upsets

The research performed and the results obtained at the Laboratory for Radiation Studies, Prairie View A&M University and Texas A&I University, on the problem of Single Events Upsets, the various schemes employed to limit them and the effects they have on the reliability and fault tolerance at the systems level, such as robotic systems are reviewed

A Read-Decoupled Gated-Ground SRAM Architecture for Low-Power Embedded Memories

In order to meet the incessantly growing demand of performance, the amount of embedded or on-chip memory in microprocessors and systems-on-chip (SOC) is increasing. As much as 70% of the chip area is now dedicated to the embedded memory, which is primarily realized by the static random access memory (SRAM). Because of the large size of the SRAM, its yield and leakage power consumption dominate the overall yield and leakage power consumption of the chip. However, as the CMOS technology continues to scale in the sub-65 nanometer regime to reduce the transistor cost and the dynamic power, it poses a number of challenges on the SRAM design. In this thesis, we address these challenges and propose cell-level and architecture level solutions to increase the yield and reduce the leakage power consumption of the SRAM in nanoscale CMOS technologies. The conventional six transistor (6T) SRAM cell inherently suffers from a trade-off between the read stability and write-ability because of using the same bit line pair for both the read and write operations. An optimum design at a given process and voltage condition is a key to ensuring the yield and reliability of the SRAM. However, with technology scaling, process-induced variations in the transistor dimensions and electrical parameters coupled with variation in the operating conditions make it difficult to achieve a reasonably high yield. In this work, a gated SRAM architecture based on a seven transistor (7T) SRAM bit-cell is proposed to address these concerns. The proposed cell decouples the read bit line from the write bit lines. As a result, the storage node is not affected by any read induced noise during the read operation. Consequently, the proposed cell shows higher data stability and yield under varying process, voltage, and temperature (PVT) conditions. A single-ended sense amplifier is also presented to read from the proposed 7T cell while a unique write mechanism is used to reduce the write power to less than half of the write power of the conventional 6T cell. The proposed cell consumes similar silicon area and leakage power as the 6T cell when laid out and simulated using a commercial 65-nm CMOS technology. However, as much as 77% reduction in leakage power can be achieved by coupling the 7T cell with the column virtual grounding (CVG) technique, where a non-zero voltage is applied to the source terminals of driver NMOS transistors in the cell. The CVG technique also enables implementing multiple words per row, which is a key requirement for memories to avoid multiple-bit data upset in the event of radiation induced single event upset or soft error. In addition, the proposed cell inherently has a 30% larger soft error critical charge, making its soft error rate (SER) less than the half of that of the 6T cell

A 28-nm 32Kb SRAM For Low-VMIN Applications Using Write and Read Assist Techniques

In this paper new write and read assist techniques, reduced coupling signal negative bitline (RCS-NBL) and low power disturbance noise reduction (LP-DNR) of 6T static random-access memory (SRAM) to improve its minimal supply voltage (VMIN), have been presented. To observe the improvements in VMIN and power consumption of SRAM with the help of proposed assist techniques, a 32 Kb capacity SRAM, with 128 words of 256 bits width, is designed and simulated in 28-nm bulk CMOS technology. New RCS-NBL scheme, shows an improvement in SRAM write VMIN by 295 mV and also reduces overstress on pass transistor (PG) of the selected bitcell by 40 mV. Proposed LP-DNR scheme demonstrates an improvement in SRAM read VMIN by 35 mV and also shows a saving of the power loss in the existing DNR scheme during the read access which occurs due to continuous flow of current from the cross coupled latch to the discharge block path after the bitlines have settled. The static power consumption of this SRAM macro is improved by 48.9 % and 11.7 % while dynamic power by 91.7 % and 8.1 % with the help of proposed write and read assist techniques respectively. Area overheads of these proposed RCS-NBL and LP-DNR assist techniques for this macro are less than 0.79 % and 3.70 % respectively

Robust Circuit Design for Low-Voltage VLSI.

Voltage scaling is an effective way to reduce the overall power consumption, but the major challenges in low voltage operations include performance degradation and reliability issues due to PVT variations. This dissertation discusses three key circuit components that are critical in low-voltage VLSI. Level converters must be a reliable interface between two voltage domains, but the reduced on/off-current ratio makes it extremely difficult to achieve robust conversions at low voltages. Two static designs are proposed: LC2 adopts a novel pulsed-operation and modulates its pull-up strength depending on its state. A 3-sigma robustness is guaranteed using a current margin plot; SLC inherently reduces the contention by diode-insertion. Improvements in performance, power, and robustness are measured from 130nm CMOS test chips. SRAM is a major bottleneck in voltage-scaling due to its inherent ratioed-bitcell design. The proposed 7T SRAM alleviates the area overhead incurred by 8T bitcells and provides robust operation down to 0.32V in 180nm CMOS test chips with 3.35fW/bit leakage. Auto-Shut-Off provides a 6.8x READ energy reduction, and its innate Quasi-Static READ has been demonstrated which shows a much improved READ error rate. A use of PMOS Pass-Gate improves the half-select robustness by directly modulating the device strength through bitline voltage. Clocked sequential elements, flip-flops in short, are ubiquitous in today’s digital systems. The proposed S2CFF is static, single-phase, contention-free, and has the same number of devices as in TGFF. It shows a 40% power reduction as well as robust low-voltage operations in fabricated 45nm SOI test chips. Its simple hold-time path and the 3.4x improvement in 3-sigma hold-time is presented. A new on-chip flip-flop testing harness is also proposed, and measured hold-time variations of flip-flops are presented.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/111525/1/yejoong_1.pd

Subthreshold SRAM Design for Energy Efficient Applications in Nanometric CMOS Technologies

Embedded SRAM circuits are vital components in a modern system on chip (SOC) that can occupy up to 90% of the total area. Therefore, SRAM circuits heavily affect SOC performance, reliability, and yield. In addition, most of the SRAM bitcells are in standby mode and significantly contribute to the total leakage current and leakage power consumption. The aggressive demand in portable devices and billions of connected sensor networks requires long battery life. Therefore, careful design of SRAM circuits with minimal power consumption is in high demand. Reducing the power consumption is mainly achieved by reducing the power supply voltage in the idle mode. However, simply reducing the supply voltage imposes practical limitations on SRAM circuits such as reduced static noise margin, poor write margin, reduced number of cells per bitline, and reduced bitline sensing margin that might cause read/write failures. In addition, the SRAM bitcell has contradictory requirements for read stability and writability. Improving the read stability can cause difficulties in a write operation or vice versa. In this thesis, various techniques for designing subthreshold energy-efficient SRAM circuits are proposed. The proposed techniques include improvement in read margin and write margin, speed improvement, energy consumption reduction, new bitcell architecture and utilizing programmable wordline boosting. A programmable wordline boosting technique is exploited on a conventional 6T SRAM bitcell to improve the operational speed. In addition, wordline boosting can reduce the supply voltage while maintaining the operational frequency. The reduction of the supply voltage allows the memory macro to operate with reduced power consumption. To verify the design, a 16-kb SRAM was fabricated using the TSMC 65 nm CMOS technology. Measurement results show that the maximum operational frequency increases up to 33.3% when wordline boosting is applied. Besides, the supply voltage can be reduced while maintaining the same frequency. This allows reducing the energy consumption to be reduced by 22.2%. The minimum energy consumption achieved is 0.536 fJ/b at 400 mV. Moreover, to improve the read margin, a 6T bitcell SRAM with a PMOS access transistor is proposed. Utilizing a PMOS access transistor results in lower zero level degradation, and hence higher read stability. In addition, the access transistor connected to the internal node holding V DD acts as a stabilizer and counterbalances the effect of zero level degradation. In order to improve the writability, wordline boosting is exploited. Wordline boosting also helps to compensate for the lower speed of the PMOS access transistor compared to a NMOS transistor. To verify our design, a 2kb SRAM is fabricated in the TSMC 65 nm CMOS technology. Measurement results show that the maximum operating frequency of the test chip is at 3.34 MHz at 290 mV. The minimum energy consumption is measured as 1.1 fJ/b at 400 mV

Implementation Of Write Assist Technique On Low Voltage Distributed Memory

In scaled technology nodes and scaled supply voltages, the SRAM write ability is being degraded and becomes a critical design concern. Various write assist techniques are developed to improve SRAM write ability. In this study, an improved write assist technique that implements the conventional boosted word-line voltage idea on the Dual-VT SRAM cell is proposed. By adopting the low threshold voltage write access transistors in the proposed technique, the comparable write access time as the conventional technique could be achieved with the lower boosted voltage. The lower boosted voltage on word-line drivers could help in static and dynamic power reductions. However, the proposed technique has drawback of higher static power on SRAM cell due to the adoption of low threshold voltage transistor. The SPICE simulation has been performed to evaluate the write performance and power consumption of the conventional and proposed techniques for comparative study. The simulation results have shown that a lower boosted voltage could be applied on lower threshold voltage write access transistor with 1% to 2% improvement as compared to the conventional technique. The boosted voltages for Std-VT, Low-VT and Ultra-Low-VT write access transistors are 1.00V, 0.94V and 0.90V respectively. When SRAM write operation is activated, there is an average of 6% total power reduction observed with the implementation of Low-VT write access transistor. The implementation of Ultra-Low-VT write access transistor produces 10% of total power reduction. When SRAM write operation is inactivated, the Low-VT write access transistor implementation could save 7% total power consumption. However, the implementation of Ultra-Low-VT write access transistor causes up to 4% total power increment. As a result, the proposed write assist technique is suitable for the low voltage distributed memory in the applications of high speed and high activity of memory write operation

Design techniques for dense embedded memory in advanced CMOS technologies

University of Minnesota Ph.D. dissertation. February 2012. Major: Electrical Engineering. Advisor: Chris H. Kim. 1 computer file (PDF); viii, 116 pages.On-die cache memory is a key component in advanced processors since it can boost micro-architectural level performance at a moderate power penalty. Demand for denser memories only going to increase as the number of cores in a microprocessor goes up with technology scaling. A commensurate increase in the amount of cache memory is needed to fully utilize the larger and more powerful processing units. 6T SRAMs have been the embedded memory of choice for modern microprocessors due to their logic compatibility, high speed, and refresh-free operation. However, the relatively large cell size and conflicting requirements for read and write make aggressive scaling of 6T SRAMs challenging in sub-22 nm. In this dissertation, circuit techniques and simulation methodologies are presented to demonstrate the potential of alternative options such as gain cell eDRAMs and spin-torque-transfer magnetic RAMs (STT-MRAMs) for high density embedded memories.Three unique test chip designs are presented to enhance the retention time and access speed of gain cell eDRAMs. Proposed bit-cells utilize preferential boostings, beneficial couplings, and aggregated cell leakages for expanding signal window between data `1' and `0'. The design space of power-delay product can be further enhanced with various assist schemes that harness the innate properties of gain cell eDRAMs. Experimental results from the test chips demonstrate that the proposed gain cell eDRAMs achieve overall faster system performances and lower static power dissipations than SRAMs in a generic 65 nm low-power (LP) CMOS process. A magnetic tunnel junction (MTJ) scaling scenario and an efficient HSPICE simulation methodology are proposed for exploring the scalability of STT-MRAMs under variation effects from 65 nm to 8 nm. A constant JC0*RA/VDD scaling method is adopted to achieve optimal read and write performances of STT-MRAMs and thermal stabilities for a 10 year retention are achieved by adjusting free layer thicknesses as well as projecting crystalline anisotropy improvements. Studies based on the proposed methodology show that in-plane STT-MRAM will outperform SRAM from 15 nm node, while its perpendicular counterpart requires further innovations in MTJ material properties in order to overcome the poor write performance from 22 nm node

Embracing Low-Power Systems with Improvement in Security and Energy-Efficiency

As the economies around the world are aligning more towards usage of computing systems, the global energy demand for computing is increasing rapidly. Additionally, the boom in AI based applications and services has already invited the pervasion of specialized computing hardware architectures for AI (accelerators). A big chunk of research in the industry and academia is being focused on providing energy efficiency to all kinds of power hungry computing architectures. This dissertation adds to these efforts. Aggressive voltage underscaling of chips is one the effective low power paradigms of providing energy efficiency. This dissertation identifies and deals with the reliability and performance problems associated with this paradigm and innovates novel energy efficient approaches. Specifically, the properties of a low power security primitive have been improved and, higher performance has been unlocked in an AI accelerator (Google TPU) in an aggressively voltage underscaled environment. And, novel power saving opportunities have been unlocked by characterizing the usage pattern of a baseline TPU with rigorous mathematical analysis