5 research outputs found
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Όλ¬Έ (λ°μ¬)-- μμΈλνκ΅ λνμ : μ κΈ°Β·μ»΄ν¨ν°κ³΅νλΆ, 2017. 2. κΉμ¬ν.A PVT-insensitive-bandwidth PLL and a chirp frequency synthesizer PLL are proposed using a constant-relative-gain digitally-controlled oscillator (DCO), a constant-gain time-to-digital converter (TDC), and a simple digital loop filter (DLF) without an explicit calibration or additional circuit components.
A digital LC-PLL that realizes a PVT-insensitive loop bandwidth (BW) by using the constant-relative-gain LC-DCO and constant-gain TDC is proposed. In other words, based on ratiometric circuit designs, the LC-DCO can make a fixed percent change to its frequency for a unit change in its digital input and the TDC can maintain a fixed range and resolution measured in reference unit intervals (UIs) across PVT variations. With such LC-DCO and TDC, the proposed PLL can realize a bandwidth which is a constant fraction of the reference frequency even with a simple proportional-integral digital loop filter without any explicit calibration loops. The prototype digital LC-PLL fabricated in a 28-nm CMOS demonstrates a frequency range of 8.38~9.34 GHz and 652-fs,rms integrated jitter from 10-kHz to 1-GHz at 8.84-GHz while dissipating 15.2-mW and occupying 0.24-mm^2. Also, the PLL across three different die samples and supply voltage ranging from 1.0 to 1.2V demonstrates a nearly constant BW at 822-kHz with the variation of Β±4.25-% only.
A chirp frequency synthesizer PLL (FS-PLL) that is capable of precise triangular frequency modulation using type-III digital LC-PLL architecture for X-band FMCW imaging radar is proposed. By employing a phase-modulating two-point modulation (TPM), constant-gain TDC, and a simple second-order DLF with polarity-alternating frequency ramp estimator, the PLL achieves a gain self-tracking TPM realizing a frequency chirp with fast chirp slope (=chirp BW/chirp period) without increasing frequency errors around the turn-around points, degrading the effective resolution achievable. A prototype chirp FS-PLL fabricated in a 65nm CMOS demonstrates that the PLL can generate a precise triangular chirp profile centered at 8.9-GHz with 940-MHz bandwidth and 28.8-us period with only 1.9-MHz,rms frequency error including the turn-around points and 14.8-mW power dissipation. The achieved 32.63-MHz/us chirp slope is higher than that of FMCW FS-PLLs previously reported by 2.6x.CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 THESIS ORGANIZATION 5
CHAPTER 2 CONVENTIONAL PHASE-LOCKED LOOP 7
2.1 CHARGE-PUMP PLL 7
2.1.1 OPERATING PRINCIPLE 7
2.1.2 LOOP DYNAMICS 9
2.2 DIGITAL PLL 10
2.2.1 OPERATING PRINCIPLE 11
2.2.2 LOOP DYNAMICS 12
CHAPTER 3 VARIATIONS ON PHASE-LOCKED LOOP 14
3.1 OSCILLATOR GAIN VARIATION 14
3.1.1 RING VOLTAGE-CONTROLLED OSCILLATOR 15
3.1.2 LC VOLTAGE-CONTROLLED OSCILLATOR 17
3.1.3 LC DIGITALLY-CONTROLLED OSCILLATOR 19
3.2 PHASE DETECTOR GAIN VARIATION 20
3.2.1 LINEAR PHASE DETECTOR 20
3.2.2 LINEAR TIME-TO-DIGITAL CONVERTER 21
CHAPTER 4 PROPOSED DCO AND TDC FOR CALIBRATION-FREE PLL 23
4.1 DIGTALLY-CONTROLLED OSCILLATOR (DCO) 25
4.1.1 OVERVIEW 24
4.1.2 CONSTANT-RELATIVE-GAIN DCO 26
4.2 TIME-TO-DIGITAL CONVERTER (TDC) 28
4.2.1 OVERVIEW 28
4.2.2 CONSTANT-GAIN TDC 30
CHAPTER 5 PVT-INSENSITIVE-BANDWIDTH PLL 35
5.1 OVERVIEW 36
5.2 PRIOR WORKS 37
5.3 PROPOSED PVT-INSENSITIVE-BANDWIDTH PLL 39
5.4 CIRCUIT IMPLEMENTATION 41
5.4.1 CAPACITOR-TUNED LC-DCO 41
5.4.2 TRANSFORMER-TUNED LC-DCO 45
5.4.3 OVERSAMPLING-BASED CONSTANT-GAIN TDC 49
5.4.4 PHASE DIGITAL-TO-ANALOG CONVERTER 52
5.4.5 DIGITAL LOOP FILTER 54
5.4.6 FREQUENCY DIVIDER 55
5.4.7 BANG-BANG PHASE-FREQUENCY DETECTOR 56
5.5 CELL-BASED DESIGN FLOW 57
5.6 MEASUREMENT RESULTS 58
CHAPTER 6 CHIRP FREQUENCY SYNTHESIZER PLL 66
6.1 OVERVIEW 67
6.2 PRIOR WORKS 71
6.3 PROPOSED CHIRP FREQUENCY SYNTHESIZER PLL 75
6.4 CIRCUIT IMPLEMENTATION 83
6.4.1 SECOND-ORDER DIGITAL LOOP FILTER 83
6.4.2 PHASE MODULATOR 84
6.4.3 CONSTANT-GAIN TDC 85
6.4.4 VRACTOR-BASED LC-DCO 87
6.4.5 OVERALL CLOCK CHAIN 90
6.5 MEASUREMENT RESULTS 91
6.6 SIGNAL-TO-NOISE RATIO OF RADAR 98
CHAPTER 7 CONCLUSION 100
BIBLIOGRAPHY 102
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We focus on Time-to-Digital Converters (TDC), one of the crucial building blocks in TD circuits. A novel algorithmic architecture is proposed based on a binary search algorithm and validated with both simulation and fabricated silicon. An all-digital structure Time-difference Amplifier (TDA) is designed and implemented to make FPGA and other all-digital implementations for TDC and related TD circuits feasible. Besides, we propose an all-digital timing measurement circuit based on the process variation from CMOS fabrication: PVTMC, which achieves a high measurement resolution:
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High Performance Local Oscillator Design for Next Generation Wireless Communication
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The focus of this thesis is to address challenges in the LO path design for next-generation high performance wireless radios. These challenges include (1) Congested spectrum at low radio frequency (RF) below 5GHz (2) Continuing miniaturization of integrated wireless radio, and (3) Fiber-fast (>10Gb/s) mm-wave wireless communication.
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eration scheme for possible use in sweeping LO-based spectrum analysis. It follows by intro- duction of the proposed fast-hopping LO architecture, its implementation and measurement results of the validated prototype. Chapter 3 proposes an embedded phase-shifting LO-path design for wideband RF self-interference cancellation for full-duplex radio. It demonstrates a synergistic design between the LO path and signal to perform self-interference cancellation.
To address the challenge of continuing miniaturization of integrated wireless radio, ring oscillator-based frequency synthesizer is an attractive candidate due to its compactness. Chapter 4 discussed the difficulty associated with implementing a Phase-Locked Loop (PLL) with ultra-small form-factor. It further proposes the concept sub-sampling PLL with time- based loop filter to address these challenges. A 65nm CMOS prototype and its measurement result are presented for validation of the concept.
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Finally, Chapter 6 presents the conclusion of this thesis
Probabilistic modeling for single-photon lidar
Lidar is an increasingly prevalent technology for depth sensing, with applications including scientific measurement and autonomous navigation systems. While conventional systems require hundreds or thousands of photon detections per pixel to form accurate depth and reflectivity images, recent results for single-photon lidar (SPL) systems using single-photon avalanche diode (SPAD) detectors have shown accurate images formed from as little as one photon detection per pixel, even when half of those detections are due to uninformative ambient light. The keys to such photon-efficient image formation are two-fold: (i) a precise model of the probability distribution of photon detection times, and (ii) prior beliefs about the structure of natural scenes. Reducing the number of photons needed for accurate image formation enables faster, farther, and safer acquisition. Still, such photon-efficient systems are often limited to laboratory conditions more favorable than the real-world settings in which they would be deployed.
This thesis focuses on expanding the photon detection time models to address challenging imaging scenarios and the effects of non-ideal acquisition equipment. The processing derived from these enhanced models, sometimes modified jointly with the acquisition hardware, surpasses the performance of state-of-the-art photon counting systems.
We first address the problem of high levels of ambient light, which causes traditional depth and reflectivity estimators to fail. We achieve robustness to strong ambient light through a rigorously derived window-based censoring method that separates signal and background light detections. Spatial correlations both within and between depth and reflectivity images are encoded in superpixel constructions, which fill in holes caused by the censoring. Accurate depth and reflectivity images can then be formed with an average of 2 signal photons and 50 background photons per pixel, outperforming methods previously demonstrated at a signal-to-background ratio of 1.
We next approach the problem of coarse temporal resolution for photon detection time measurements, which limits the precision of depth estimates. To achieve sub-bin depth precision, we propose a subtractively-dithered lidar implementation, which uses changing synchronization delays to shift the time-quantization bin edges. We examine the generic noise model resulting from dithering Gaussian-distributed signals and introduce a generalized Gaussian approximation to the noise distribution and simple order statistics-based depth estimators that take advantage of this model. Additional analysis of the generalized Gaussian approximation yields rules of thumb for determining when and how to apply dither to quantized measurements. We implement a dithered SPL system and propose a modification for non-Gaussian pulse shapes that outperforms the Gaussian assumption in practical experiments. The resulting dithered-lidar architecture could be used to design SPAD array detectors that can form precise depth estimates despite relaxed temporal quantization constraints.
Finally, SPAD dead time effects have been considered a major limitation for fast data acquisition in SPL, since a commonly adopted approach for dead time mitigation is to operate in the low-flux regime where dead time effects can be ignored. We show that the empirical distribution of detection times converges to the stationary distribution of a Markov chain and demonstrate improvements in depth estimation and histogram correction using our Markov chain model. An example simulation shows that correctly compensating for dead times in a high-flux measurement can yield a 20-times speed up of data acquisition. The resulting accuracy at high photon flux could enable real-time applications such as autonomous navigation