A Fully-Integrated Shift-Register DLDO Using Pull-Up and Pull-Down Devices

The digital low-drop-out regulator (DLDO) regulates its output voltage and provides a fast transient response during a load change. DLDO is an essential part for managing power consumption of multiple supply voltage domains in modern system-on-chip (SOC) designs. One of the conventional DLDO designs uses a shift register (SR) to regulate the output voltage by controlling shift directions of the output bits. The shift register changes the output bits sequentially, hence providing high accuracy in steady state. However, due to this characteristic, the SR-based DLDO cannot provide a fast transient response during a load change. Higher clock frequency during the load transient can solve the problem, but it results in higher power consumption. To overcome this disadvantage, this paper offers a fully-integrated SR-based DLDO with pull-up and pull-down switches. It discusses optimization of the pull-up and pull-down switch size in detail