A Bang-Bang All-Digital PLL for Frequency Synthesis

abstract: Phase locked loops are an integral part of any electronic system that requires a clock signal and find use in a broad range of applications such as clock and data recovery circuits for high speed serial I/O and frequency synthesizers for RF transceivers and ADCs. Traditionally, PLLs have been primarily analog in nature and since the development of the charge pump PLL, they have almost exclusively been analog. Recently, however, much research has been focused on ADPLLs because of their scalability, flexibility and higher noise immunity. This research investigates some of the latest all-digital PLL architectures and discusses the qualities and tradeoffs of each. A highly flexible and scalable all-digital PLL based frequency synthesizer is implemented in 180 nm CMOS process. This implementation makes use of a binary phase detector, also commonly called a bang-bang phase detector, which has potential of use in high-speed, sub-micron processes due to the simplicity of the phase detector which can be implemented with a simple D flip flop. Due to the nonlinearity introduced by the phase detector, there are certain performance limitations. This architecture incorporates a separate frequency control loop which can alleviate some of these limitations, such as lock range and acquisition time.Dissertation/ThesisM.S. Electrical Engineering 201

Techniques for high-performance digital frequency synthesis and phase control

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references (p. 183-190).This thesis presents a 3.6-GHz, 500-kHz bandwidth digital [delta][sigma] frequency synthesizer architecture that leverages a recently invented noise-shaping time-to-digital converter (TDC) and an all-digital quantization noise cancellation technique to achieve excellent in-band and out-of-band phase noise, respectively. In addition, a passive digital-to-analog converter (DAC) structure is proposed as an efficient interface between the digital loop filter and a conventional hybrid voltage-controlled oscillator (VCO) to create a digitally-controlled oscillator (DCO). An asynchronous divider structure is presented which lowers the required TDC range and avoids the divide-value-dependent delay variation. The prototype is implemented in a 0.13-am CMOS process and its active area occupies 0.95 mm². Operating under 1.5 V, the core parts, excluding the VCO output buffer, dissipate 26 mA. Measured phase noise at 3.67 GHz achieves -108 dBc/Hz and -150 dBc/Hz at 400 kHz and 20 MHz, respectively. Integrated phase noise at this carrier frequency yields 204 fs of jitter (measured from 1 kHz to 40 MHz). In addition, a 3.2-Gb/s delay-locked loop (DLL) in a 0.18-[mu]m CMOS for chip-tochip communications is presented. By leveraging the fractional-N synthesizer technique, this architecture provides a digitally-controlled delay adjustment with a fine resolution and infinite range. The provided delay resolution is less sensitive to the process, voltage, and temperature variations than conventional techniques. A new [delta][sigma] modulator enables a compact and low-power implementation of this architecture. A simple bang-bang detector is used for phase detection. The prototype operates at a 1.8-V supply voltage with a current consumption of 55 mA. The phase resolution and differential rms clock jitter are 1.4 degrees and 3.6 ps, respectively.by Chun-Ming Hsu.Ph.D

On-Chip Analog Circuit Design Using Built-In Self-Test and an Integrated Multi-Dimensional Optimization Platform

Nowadays, the rapid development of system-on-chip (SoC) market introduces tremendous complexity into the integrated circuit (IC) design. Meanwhile, the IC fabrication process is scaling down to allow higher density of integration but makes the chips more sensitive to the process-voltage-temperature (PVT) variations. A successful IC product not only imposes great pressure on the IC designers, who have to handle wider variations and enforce more design margins, but also challenges the test procedure, leading to more check points and longer test time. To relax the designers’ burden and reduce the cost of testing, it is valuable to make the IC chips able to test and tune itself to some extent. In this dissertation, a fully integrated in-situ design validation and optimization (VO) hardware for analog circuits is proposed. It implements in-situ built-in self-test (BIST) techniques for analog circuits. Based on the data collected from BIST, the error between the measured and the desired performance of the target circuit is evaluated using a cost function. A digital multi-dimensional optimization engine is implemented to adaptively adjust the analog circuit parameters, seeking the minimum value of the cost function and achieving the desired performance. To verify this concept, study cases of a 2nd/4th active-RC band-pass filter (BPF) and a 2nd order Gm-C BPF, as well as all BIST and optimization blocks, are adopted on-chip. Apart from the VO system, several improved BIST techniques are also proposed in this dissertation. A single-tone sinusoidal waveform generator based on a finite-impulse-response (FIR) architecture, which utilizes an optimization algorithm to enhance its spur free dynamic range (SFDR), is proposed. It achieves an SFDR of 59 to 70 dBc from 150 to 850 MHz after the optimization procedure. A low-distortion current-steering two-tone sinusoidal signal synthesizer based on a mixing-FIR architecture is also proposed. The two-tone synthesizer extends the FIR architecture to two stages and implements an up-conversion mixer to generate the two tones, achieving better than -68 dBc IM3 below 480 MHz LO frequency without calibration. Moreover, an on-chip RF receiver linearity BIST methodology for continuous and discrete-time hybrid baseband chain is proposed. The proposed receiver chain implements a charge-domain FIR filter to notch the two excitation signals but expose the third order intermodulation (IM3) tones. It simplifies the linearity measurement procedure–using a power detector is enough to analyze the receiver’s linearity. Finally, a low cost fully digital built-in analog tester for linear-time-invariant (LTI) analog blocks is proposed. It adopts a time-to-digital converter (TDC) to measure the delays corresponded to a ramp excitation signal and is able to estimate the pole or zero locations of a low-pass LTI system

Design and investigation of nanometric integrated circuits for all-digital frequency synthesisers

Disertacijoje nagrinėjami daugiajuosčių dažnio sintezatorių blokai, modeliai bei jų kūrimas taikant nanometrines integrinių grandynų technologijas. Iškeliama ir įrodoma hipotezė, kad taikant nanometrines technologijas visiškai skaitmeniniai dažnio sintezatoriai įgalina gauti parametrus, reikiamus daugiajuosčiams belai- džio ryšio siųstuvams-imtuvams. Darbo tikslas – sukurti visiškai skaitmeninio dažnio sintezatoriaus blokus, kuriuos naudojant galima pasiekti reikiamus sinte- zatoriaus, skirto daugiajuosčiams belaidžio ryšio siųstuvams-imtuvams, paramet- rus taikant nanometrines integrinių grandynų gamybos technologijas. Darbe išsp- ręsti tokie uždaviniai: ištirtos dažnio sintezatorių struktūros ir sukurta struktūra, tinkama įgyvendinti taikant nanometrines technologijas, sukurti ir ištirti siūlomos struktūros sintezatorių sudarančių blokų modeliai ir integriniai grandynai. Disertaciją sudaro įvadas, trys skyriai, bendrosios išvados, naudotos literatū- ros ir autoriaus publikacijų disertacijos tema sąrašai ir keturi priedai. Įvadiniame skyriuje aptariama tiriamoji problema, darbo aktualumas, aprašo- mas tyrimų objektas, formuluojamas darbo tikslas bei uždaviniai, aprašoma ty- rimų metodika, darbo mokslinis naujumas, darbo rezultatų praktinė reikšmė, gi- namieji teiginiai bei disertacijos struktūra. Pirmajame skyriuje apžvelgiamos dažnio sintezatorių rūšys, aprašomi pag- rindiniai dažnio sintezatorių parametrai ir dažniausiai naudojamos kokybės funk- cijos. Apžvelgiami dažnio sintezatorių modeliai ir jų veikimas fazės ir dažnio sri- tyse. Aprašomi visiškai skaitmeninio dažnio sintezatoriaus triukšmų šaltiniai. Skyriaus pabaigoje suformuluojami disertacijos uždaviniai. Antrajame skyriuje pasiūlyta ir taikoma nauja kokybės funkcija, leidžianti at- likti daugiajuosčių dažnio sintezatorių palyginamąją analizę. Iškeliami reikalavi- mai pagrindiniams sintezatoriaus blokams, nagrinėjami laikinio skaitmeninio kei- tiklio skiriamosios gebos didinimo būdai, sukurtas naujas laikinio skaitmeninio keitiklio modelis. Siūloma dažnio sintezatoriaus struktūra daugiajuosčiams siųs- tuvams-imtuvams. Trečiajame skyriuje pagal iškeltus reikalavimus daugiajuosčio dažnio sinte- zatoriaus blokams, taikant kompiuterinių skaičiavimų ir eksperimentinius meto- dus yra kuriami ir tiriami laikinio skaitmeninio keitiklio, skaitmeniniu būdu val- domo generatoriaus bei skaitmeninio filtro integriniai grandynai. Disertacijos tema yra atspausdinti 7 moksliniai straipsniai: 4 – mokslo žurna- luose, įtrauktuose į Clarivate Analytics Web of Science duomenų bazę, 1 – tarp- tautinių konferencijų medžiagoje, įtrauktoje į Clarivate Analytics Proceedings duomenų bazę, 2 – mokslo žurnaluose, referuojamuose kitose tarptautinėse duo- menų bazėse. Disertacijoje atliktų tyrimų rezultatai buvo paskelbti devyniose mokslinėse konferencijose Lietuvoje ir užsienyje

Development of a Full-Field Time-of-Flight Range Imaging System

A full-field, time-of-flight, image ranging system or 3D camera has been developed from a proof-of-principle to a working prototype stage, capable of determining the intensity and range for every pixel in a scene. The system can be adapted to the requirements of various applications, producing high precision range measurements with sub-millimetre resolution, or high speed measurements at video frame rates. Parallel data acquisition at each pixel provides high spatial resolution independent of the operating speed. The range imaging system uses a heterodyne technique to indirectly measure time of flight. Laser diodes with highly diverging beams are intensity modulated at radio frequencies and used to illuminate the scene. Reflected light is focused on to an image intensifier used as a high speed optical shutter, which is modulated at a slightly different frequency to that of the laser source. The output from the shutter is a low frequency beat signal, which is sampled by a digital video camera. Optical propagation delay is encoded into the phase of the beat signal, hence from a captured time variant intensity sequence, the beat signal phase can be measured to determine range for every pixel in the scene. A direct digital synthesiser (DDS) is designed and constructed, capable of generating up to three outputs at frequencies beyond 100 MHz with the relative frequency stability in excess of nine orders of magnitude required to control the laser and shutter modulation. Driver circuits were also designed to modulate the image intensifier photocathode at 50 Vpp, and four laser diodes with a combined power output of 320 mW, both over a frequency range of 10-100 MHz. The DDS, laser, and image intensifier response are characterised. A unique method of measuring the image intensifier optical modulation response is developed, requiring the construction of a pico-second pulsed laser source. This characterisation revealed deficiencies in the measured responses, which were mitigated through hardware modifications where possible. The effects of remaining imperfections, such as modulation waveform harmonics and image intensifier irising, can be calibrated and removed from the range measurements during software processing using the characterisation data. Finally, a digital method of generating the high frequency modulation signals using a FPGA to replace the analogue DDS is developed, providing a highly integrated solution, reducing the complexity, and enhancing flexibility. In addition, a novel modulation coding technique is developed to remove the undesirable influence of waveform harmonics from the range measurement without extending the acquisition time. When combined with a proposed modification to the laser illumination source, the digital system can enhance range measurement precision and linearity. From this work, a flexible full-field image ranging system is successfully realised. The system is demonstrated operating in a high precision mode with sub-millimetre depth resolution, and also in a high speed mode operating at video update rates (25 fps), in both cases providing high (512 512) spatial resolution over distances of several metres

HIGH PERFORMANCE CMOS WIDE-BAND RF FRONT-END WITH SUBTHRESHOLD OUT OF BAND SENSING

In future, the radar/satellite wireless communication devices must support multiple standards and should be designed in the form of system-on-chip (SoC) so that a significant reduction happen on cost, area, pins, and power etc. However, in such device, the design of a fully on-chip CMOS wideband receiver front-end that can process several radar/satellite signal simultaneously becomes a multifold complex problem. Further, the inherent high-power out-of-band (OB) blockers in radio spectrum will make the receiver more non-linear, even sometimes saturate the receiver. Therefore, the proper blocker rejection techniques need to be incorporated. The primary focus of this research work is the development of a CMOS high-performance low noise wideband receiver architecture with a subthreshold out of band sensing receiver. Further, the various reconfigurable mixer architectures are proposed for performance adaptability of a wideband receiver for incoming standards. Firstly, a high-performance low- noise bandwidthenhanced fully differential receiver is proposed. The receiver composed of a composite transistor pair noise canceled low noise amplifier (LNA), multi-gate-transistor (MGTR) trans-conductor amplifier, and passive switching quad followed by Tow Thomas bi-quad second order filter based tarns-impedance amplifier. An inductive degenerative technique with low-VT CMOS architecture in LNA helps to improve the bandwidth and noise figure of the receiver. The full receiver system is designed in UMC 65nm CMOS technology and measured. The packaged LNA provides a power gain 12dB (including buffer) with a 3dB bandwidth of 0.3G – 3G, noise figure of 1.8 dB having a power consumption of 18.75mW with an active area of 1.2mm*1mm. The measured receiver shows 37dB gain at 5MHz IF frequency with 1.85dB noise figure and IIP3 of +6dBm, occupies 2mm*1.2mm area with 44.5mW of power consumption. Secondly, a 3GHz-5GHz auxiliary subthreshold receiver is proposed to estimate the out of blocker power. As a redundant block in the system, the cost and power minimization of the auxiliary receiver are achieved via subthreshold circuit design techniques and implementing the design in higher technology node (180nm CMOS). The packaged auxiliary receiver gives a voltage gain of 20dB gain, the noise figure of 8.9dB noise figure, IIP3 of -10dBm and 2G-5GHz bandwidth with 3.02mW power consumption. As per the knowledge, the measured results of proposed main-high-performancereceiver and auxiliary-subthreshold-receiver are best in state of art design. Finally, the various viii reconfigurable mixers architectures are proposed to reconfigure the main-receiver performance according to the requirement of the selected communication standard. The down conversion mixers configurability are in the form of active/passive and Input (RF) and output (IF) bandwidth reconfigurability. All designs are simulated in 65nm CMOS technology. To validate the concept, the active/ passive reconfigurable mixer configuration is fabricated and measured. Measured result shows a conversion gain of 29.2 dB and 25.5 dB, noise figure of 7.7 dB and 10.2 dB, IIP3 of -11.9 dBm and 6.5 dBm in active and passive mode respectively. It consumes a power 9.24mW and 9.36mW in passive and active case with a bandwidth of 1 to 5.5 GHz and 0.5 to 5.1 GHz for active/passive case respectively

TIME-DIFFERENCE CIRCUITS: METHODOLOGY, DESIGN, AND DIGITAL REALIZATION

This thesis presents innovations for a special class of circuits called Time Difference (TD) circuits. We introduce a signal processing methodology with TD signals that alters the target signal from a magnitude perspective to time interval between two time events and systematically organizes the primary TD functions abstracted from existing TD circuits and systems. The TD circuits draw attention from a broad range of application fields. In addition, highly evolved complementary metal-oxide-semiconductor (CMOS) technology suffers from various problems related to voltage and current amplitude signal processing methods. Compared to traditional analog and digital circuits, TD circuits bring several compelling features: high-resolution, high-throughput, and low-design complexity with digital integration capability. Further, the fabrication technology is advancing into the nanometer regime; the reduction in voltage headroom limits the performance of traditional analog/mixed-signal designs. All-digital design of time-difference circuit needs to be stressed to adapt to the low-cost, low-power, and high-portability applications. We focus on Time-to-Digital Converters (TDC), one of the crucial building blocks in TD circuits. A novel algorithmic architecture is proposed based on a binary search algorithm and validated with both simulation and fabricated silicon. An all-digital structure Time-difference Amplifier (TDA) is designed and implemented to make FPGA and other all-digital implementations for TDC and related TD circuits feasible. Besides, we propose an all-digital timing measurement circuit based on the process variation from CMOS fabrication: PVTMC, which achieves a high measurement resolution:

Special Topics in Information Technology

This open access book presents thirteen outstanding doctoral dissertations in Information Technology from the Department of Electronics, Information and Bioengineering, Politecnico di Milano, Italy. Information Technology has always been highly interdisciplinary, as many aspects have to be considered in IT systems. The doctoral studies program in IT at Politecnico di Milano emphasizes this interdisciplinary nature, which is becoming more and more important in recent technological advances, in collaborative projects, and in the education of young researchers. Accordingly, the focus of advanced research is on pursuing a rigorous approach to specific research topics starting from a broad background in various areas of Information Technology, especially Computer Science and Engineering, Electronics, Systems and Control, and Telecommunications. Each year, more than 50 PhDs graduate from the program. This book gathers the outcomes of the thirteen best theses defended in 2019-20 and selected for the IT PhD Award. Each of the authors provides a chapter summarizing his/her findings, including an introduction, description of methods, main achievements and future work on the topic. Hence, the book provides a cutting-edge overview of the latest research trends in Information Technology at Politecnico di Milano, presented in an easy-to-read format that will also appeal to non-specialists

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields