Tunable n-path notch filters for blocker suppression: modeling and verification

N-path switched-RC circuits can realize filters with very high linearity and compression point while they are tunable by a clock frequency. In this paper, both differential and single-ended N-path notch filters are modeled and analyzed. Closed-form equations provide design equations for the main filtering characteristics and nonidealities such as: harmonic mixing, switch resistance, mismatch and phase imbalance, clock rise and fall times, noise, and insertion loss. Both an eight-path single-ended and differential notch filter are implemented in 65-nm CMOS technology. The notch center frequency, which is determined by the switching frequency, is tunable from 0.1 to 1.2 GHz. In a 50- environment, the N-path filters provide power matching in the passband with an insertion loss of 1.4–2.8 dB. The rejection at the notch frequency is 21–24 dB,P1 db> + 2 dBm, and IIP3 > + 17 dBm

High Performance LNAs and Mixers for Direct Conversion Receivers in BiCMOS and CMOS Technologies

The trend in cellular chipset design today is to incorporate support for a larger number of frequency bands for each new chipset generation. If the chipset also supports receiver diversity two low noise amplifiers (LNAs) are required for each frequency band. This is however associated with an increase of off-chip components, i.e. matching components for the LNA inputs, as well as complex routing of the RF input signals. If balanced LNAs are implemented the routing complexity is further increased. The first presented work in this thesis is a novel multiband low noise single ended LNA and mixer architecture. The mixer has a novel feedback loop suppressing both second order distortion as well as DC-offset. The performance, verified by Monte Carlo simulations, is sufficient for a WCDMA application. The second presented work is a single ended multiband LNA with programmable integrated matching. The LNA is connected to an on-chip tunable balun generating differential RF signals for a differential mixer. The combination of the narrow band input matching and narrow band balun of the presented LNA is beneficial for suppressing third harmonic downconversion of a WLAN interferer. The single ended architecture has great advantages regarding PCB routing of the RF input signals but is on the other hand more sensitive to common mode interferers, e.g. ground, supply and substrate noise. An analysis of direct conversion receiver requirements is presented together with an overview of different LNA and mixer architectures in both BiCMOS and CMOS technology

Configurable circuits and their impact on multi-standard RF front-end architectures

This thesis studies configurable circuits and their impact on multi-standard RF front-end architectures. In particular, low-voltage low-power linear LNA and mixer topologies suitable for implementation in multi-standard front-ends are subject of the investigation. With respect to frequency and bandwidth, multi-standard front-ends can be implemented using either tunable or wideband LNA and mixer topologies. Based on the type of the LNA and mixer(s), multi-standard receiver RF front-ends can be divided into three groups. They can be (tunable) narrow-band, wide-band or combined. The advantages and disadvantages of the different multi-standard receiver RF front-ends have been discussed in detail. The partitioning between off-chip selectivity, on-chip selectivity provided by the LNA and mixer, linearity, power consumption and occupied chip area in each multi-standard RF front-end group are thoroughly investigated. A Figure of Merit (FOM) for the multi-standard receiver RF front-end has been introduced. Based on this FOM the most suitable multi-standard RF front-end group in terms of cost-effectiveness can be selected. In order to determine which multi-standard RF front-end group is the most cost-effective for a practical application, a GSM850/E-GSM/DCS/PCS/Bluetooth/WLANa/b/g multi-standard receiver RF front-end is chosen as a demonstrator. These standards are the most frequently used standards in wireless communication, and this combination of standards allows to users almost "anytime-anywhere" voice and data transfer. In order to verify these results, three demonstrators have been defined, designed and implemented, two wideband RF front-end circuits in 90nm CMOS and 65nm CMOS, and one combined multi-standard RF front-end circuit in 65nm CMOS. The proposed multi-standard demonstrators have been compared with the state-of the art narrow-band, wide-band and combined multi-standard RF front-ends. On the proposed multi-standard RF front-ends and the state-of the art multi-standard RF front-ends the proposed FOM have been applied. The comparison shows that the combined multi-standard RF front-end group is the most cost effective multi-standard group for this application

Saw-Less radio receivers in CMOS

Smartphones play an essential role in our daily life. Connected to the internet, we can easily keep in touch with family and friends, even if far away, while ever more apps serve us in numerous ways. To support all of this, higher data rates are needed for ever more wireless users, leading to a very crowded radio frequency spectrum. To achieve high spectrum efficiency while reducing unwanted interference, high-quality band-pass filters are needed. Piezo-electrical Surface Acoustic Wave (SAW) filters are conventionally used for this purpose, but such filters need a dedicated design for each new band, are relatively bulky and also costly compared to integrated circuit chips. Instead, we would like to integrate the filters as part of the entire wireless transceiver with digital smartphone hardware on CMOS chips. The research described in this thesis targets this goal. It has recently been shown that N-path filters based on passive switched-RC circuits can realize high-quality band-select filters on CMOS chips, where the center frequency of the filter is widely tunable by the switching-frequency. As CMOS downscaling following Moore’s law brings us lower clock-switching power, lower switch on-resistance and more compact metal-to-metal capacitors, N-path filters look promising. This thesis targets SAW-less wireless receiver design, exploiting N-path filters. As SAW-filters are extremely linear and selective, it is very challenging to approximate this performance with CMOS N-path filters. The research in this thesis proposes and explores several techniques for extending the linearity and enhancing the selectivity of N-path switched-RC filters and mixers, and explores their application in CMOS receiver chip designs. First the state-of-the-art in N-path filters and mixer-first receivers is reviewed. The requirements on the main receiver path are examined in case SAW-filters are removed or replaced by wideband circulators. The feasibility of a SAW-less Frequency Division Duplex (FDD) radio receiver is explored, targeting extreme linearity and compression Irequirements. A bottom-plate mixing technique with switch sharing is proposed. It improves linearity by keeping both the gate-source and gate-drain voltage swing of the MOSFET-switches rather constant, while halving the switch resistance to reduce voltage swings. A new N-path switch-RC filter stage with floating capacitors and bottom-plate mixer-switches is proposed to achieve very high linearity and a second-order voltage-domain RF-bandpass filter around the LO frequency. Extra out-of-band (OOB) rejection is implemented combined with V-I conversion and zero-IF frequency down-conversion in a second cross-coupled switch-RC N-path stage. It offers a low-ohmic high-linearity current path for out-of-band interferers. A prototype chip fabricated in a 28 nm CMOS technology achieves an in-band IIP3 of +10 dBm , IIP2 of +42 dBm, out-of-band IIP3 of +44 dBm, IIP2 of +90 dBm and blocker 1-dB gain-compression point of +13 dBm for a blocker frequency offset of 80 MHz. At this offset frequency, the measured desensitization is only 0.6 dB for a 0-dBm blocker, and 3.5 dB for a 10-dBm blocker at 0.7 GHz operating frequency (i.e. 6 and 9 dB blocker noise figure). The chip consumes 38-96 mW for operating frequencies of 0.1-2 GHz and occupies an active area of 0.49 mm2. Next, targeting to cover all frequency bands up to 6 GHz and achieving a noise figure lower than 3 dB, a mixer-first receiver with enhanced selectivity and high dynamic range is proposed. Capacitive negative feedback across the baseband amplifier serves as a blocker bypassing path, while an extra capacitive positive feedback path offers further blocker rejection. This combination of feedback paths synthesizes a complex pole pair at the input of the baseband amplifier, which is up-converted to the RF port to obtain steeper RF-bandpass filter roll-off than the conventional up-converted real pole and reduced distortion. This thesis explains the circuit principle and analyzes receiver performance. A prototype chip fabricated in 45 nm Partially Depleted Silicon on Insulator (PDSOI) technology achieves high linearity (in-band IIP3 of +3 dBm, IIP2 of +56 dBm, out-of-band IIP3 = +39 dBm, IIP2 = +88 dB) combined with sub-3 dB noise figure. Desensitization due to a 0-dBm blocker is only 2.2 dB at 1.4 GHz operating frequency. IIFinally, to demonstrate the performance of the implemented blocker-tolerant receiver chip designs, a test setup with a real mobile phone is built to verify the sensitivity of the receiver chip for different practical blocking scenarios

Blocker Tolerant Radio Architectures

Future radio platforms have to be inexpensive and deal with a variety of co- existence issues. The technology trend during the last few years is towards system- on-chip (SoC) that is able to process multiple standards re-using most of the digital resources. A major bottle-neck to this approach is the co-existence of these standards operating at different frequency bands that are hitting the receiver front-end. So the current research is focused on the power, area and performance optimization of various circuit building blocks of a radio for current and incoming standards. Firstly, a linearization technique for low noise amplifiers (LNAs) called, Robust Derivative Superposition (RDS) method is proposed. RDS technique is insensitive to Process Voltage and Temperature (P.V.T.) variations and is validated with two low noise transconductance amplifier (LNTA) designs in 0.18µm CMOS technology. Measurement results from 5 dies of a resistive terminated LNTA shows that the pro- posed method improves IM3 over 20dB for input power up to -18dBm, and improves IIP_(3) by 10dB. A 2V inductor-less broadband 0.3 to 2.8GHz balun-LNTA employing the proposed RDS linearization technique was designed and measured. It achieves noise figure of 6.5dB, IIP3 of 16.8dBm, and P1dB of 0.5dBm having a power consumption of 14.2mW. The balun LNTA occupies an active area of 0.06mm2. Secondly, the design of two high linearity, inductor-less, broadband LNTAs employing noise and distortion cancellation techniques is presented. Main design issues and the performance trade-offs of the circuits are discussed. In the fully differential architecture, the first LNTA covers 0.1-2GHz bandwidth and achieves a minimum noise figure (NFmin) of 3dB, IIP_(3) of 10dBm and a P_(1dB) of 0dBm while dissipating 30.2mW. The 2^(nd) low power bulk driven LNTA with 16mW power consumption achieves NFmin of 3.4dB, IIP3 of 11dBm and 0.1-3GHz bandwidth. Each LNTA occupy an active area of 0.06mm2 in 45nm CMOS. Thirdly, a continuous-time low-pass ∆ΣADC equipped with design techniques to provide robustness against loop saturation due to blockers is presented. Loop over- load detection and correction is employed to improve the ADC’s tolerance to blockers; a fast overload detector activates the input attenuator, maintaining the ADC in linear operation. To further improve ADC’s blocker tolerance, a minimally-invasive integrated low-pass filter that reduces the most critical adjacent/alternate channel blockers is implemented. An ADC prototype is implemented in a 90nm CMOS technology and experimentally it achieves 69dB dynamic range over a 20MHz bandwidth with a sampling frequency of 500MHz and 17.1mW of power consumption. The alternate channel blocker tolerance at the most critical frequency is as high as -5.5dBFS while the conventional feed-forward modulator becomes unstable at -23.5dBFS of blocker power. The proposed blocker rejection techniques are minimally-invasive and take less than 0.3µsec to settle after a strong agile blocker appears. Finally, a new radio partitioning methodology that gives robust analog and mixed signal radio development in scaled technology for SoC integration, and the co-design of RF FEM-antenna system is presented. Based on the proposed methodology, a CMOS RF front-end module (FEM) with power amplifier (PA), LNA and transmit/receive switch, co-designed with antenna is implemented. The RF FEM circuit is implemented in a 32nm CMOS technology. Post extracted simulations show a noise figure < 2.5dB, S_(21) of 14dB, IIP3 of 7dBm and P1dB of -8dBm for the receiver. Total power consumption of the receiver is 11.8mW from a 1V supply. On the trans- mitter side, PA achieves peak RF output power of 22.34dBm with peak power added efficiency (PAE) of 65% and PAE of 33% with linearization at -6dB power back off. Simulations show an efficiency of 80% for the miniaturized dipole antenna

RF CMOS Oscillators for Modern Wireless Applications

While mobile phones enjoy the largest production volume ever of any consumer electronics products, the demands they place on radio-frequency (RF) transceivers are particularly aggressive, especially on integration with digital processors, low area, low power consumption, while being robust against process-voltage-temperature variations. Since mobile terminals inherently operate on batteries, their power budget is severely constrained. To keep up with the ever increasing data-rate, an ever-decreasing power per bit is required to maintain the battery lifetime. The RF oscillator is the second most power-hungry block of a wireless radio (after power amplifiers). Consequently, any power reduction in an RF oscillator will greatly benefit the overall power efficiency of the cellular transceiver. Moreover, the RF oscillators' purity limits the transceiver performance. The oscillator's phase noise results in power leakage into adjacent channels in a transmit mode and reciprocal mixing in a receive mode. On the other hand, the multi-standard and multi-band transceivers that are now trending demand wide tuning range oscillators. However, broadening the oscillator’s tuning range is usually at the expense of die area (cost) or phase noise. The main goal of this book is to bring forth the exciting and innovative RF oscillator structures that demonstrate better phase noise performance, lower cost, and higher power efficiency than currently achievable. Technical topics discussed in RF CMOS Oscillators for Modern Wireless Applications include: Design and analysis of low phase-noise class-F oscillators Analyze a technique to reduce 1/f noise up-conversion in the oscillators Design and analysis of low power/low voltage oscillators Wide tuning range oscillators Reliability study of RF oscillators in nanoscale CMO

Flexible Receivers in CMOS for Wireless Communication

Consumers are pushing for higher data rates to support more services that are introduced in mobile applications. As an example, a few years ago video-on-demand was only accessed through landlines, but today wireless devices are frequently used to stream video. To support this, more flexible network solutions have merged in 4G, introducing new technical problems to the mobile terminal. New techniques are thus needed, and this dissertation explores five different ideas for receiver front-ends, that are cost-efficient and flexible both in performance and operating frequency. All ideas have been implemented in chips fabricated in 65 nm CMOS technology and verified by measurements. Paper I explores a voltage-mode receiver front-end where sub-threshold positive feedback transistors are introduced to increase the linearity in combination with a bootstrapped passive mixer. Paper II builds on the idea of 8-phase harmonic rejection, but simplifies it to a 6-phase solution that can reject noise and interferers at the 3rd order harmonic of the local oscillator frequency. This provides a good trade-off between the traditional quadrature mixer and the 8- phase harmonic rejection mixer. Furthermore, a very compact inductor-less low noise amplifier is introduced. Paper III investigates the use of global negative feedback in a receiver front-end, and also introduces an auxiliary path that can cancel noise from the main path. In paper IV, another global feedback based receiver front-end is designed, but with positive feedback instead of negative. By introducing global positive feedback, the resistance of the transistors in a passive mixer-first receiver front-end can be reduced to achieve a lower noise figure, while still maintaining input matching. Finally, paper V introduces a full receiver chain with a single-ended to differential LNA, current-mode downconversion mixers, and a baseband circuity that merges the functionalities of the transimpedance amplifier, channel-select filter, and analog-to-digital converter into one single power-efficient block