Design of Analog-to-Digital Converters with Embedded Mixing for Ultra-Low-Power Radio Receivers

In the field of radio receivers, down-conversion methods usually rely on one (or more) explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not only contribute to the overall power consumption but also have an impact on area and can compromise the receiver’s performance in terms of noise and linearity. On the other hand, most ADCs require some sort of reference signal in order to properly digitize an analog input signal. The implementation of this reference signal usually relies on bandgap circuits and reference buffers to generate a constant, stable, dc signal. Disregarding this conventional approach, the work developed in this thesis aims to explore the viability behind the usage of a variable reference signal. Moreover, it demonstrates that not only can an input signal be properly digitized, but also shifted up and down in frequency, effectively embedding the mixing operation in an ADC. As a result, ADCs in receiver chains can perform double-duty as both a quantizer and a mixing stage. The lesser known charge-sharing (CS) topology, within the successive approximation register (SAR) ADCs, is used for a practical implementation, due to its feature of “pre-charging” the reference signal prior to the conversion. Simulation results from an 8-bit CS-SAR ADC designed in a 0.13 μm CMOS technology validate the proposed technique

A CMOS DB-linear VGA with DC offset cancellation for direct-conversion receiver

Master'sMASTER OF ENGINEERIN

Data Acquisition Applications

Data acquisition systems have numerous applications. This book has a total of 13 chapters and is divided into three sections: Industrial applications, Medical applications and Scientific experiments. The chapters are written by experts from around the world, while the targeted audience for this book includes professionals who are designers or researchers in the field of data acquisition systems. Faculty members and graduate students could also benefit from the book

Design of a variable gain amplifier for an ultrawideband receiver

A fully differential CMOS variable gain amplifier (VGA) has been designed for an ultra-wideband receiver. The VGA comprises of two variable gain stages followed by a post amplifier stage. The interface between the digital control block and the analog VGA is formed by a digital-to-analog converter and an exponential voltage generator. The gain of the VGA varies dB-linearly from 0 to 52 dB with respect to the control voltage. The VGA is operated in open loop with a bandwidth greater than 500 MHz throughout the gain range to cater to the requirements of the ultra-wideband system. The noise-to-power ratio of the VGA is -23.9 dB for 1Vp-p differential input signal in the low gain setting, and the equivalent input referred noise is 1.01 V2 for the high gain setting. All three stages use common mode feedback to fix and stabilize the output DC levels at a particular voltage depending on the input common-mode requirement of the following stage. DC offset cancellation has also been incorporated to minimize the input referred DC offset caused by systematic and random mismatches in the circuit. Compensation schemes to minimize the effects of temperature, supply and process variations have been included in the design. The circuit has been designed in 0.18??m CMOS technology, and the post layout simulations are in good agreement with the schematic simulations

Energieeffiziente HF-Front-End-Schaltungsarchitekturen am Beispiel von ZigBee-Empfängern

Der Arbeit vorangestellt ist eine Literaturübersicht über die verschiedenen Empfängerarchitekturen, aus denen die homodyne Architektur als die am besten für einen energieeffizienten Empfänger wie z.B. ZigBee geeignete ausgewählt wird. Basierend auf einer Systemsimulation werden die Kennzahlen des gesamten Empfängers festgelegt und diese umgesetzt in Spezifikationen für die einzelnen Schaltungsblöcke. Aus den festgelegten Kennzahlen wird deutlich, dass im Vergleich zu anderen drahtlosen Systemen eine geringe Anforderung an das Noise Figure und die Linearität gestellt wird, aber eine hohe Anforderung der geringe Stromverbrauch darstellt. In einer weiteren Literaturübersicht werden unterschiedlichen LNA-Architekturen miteinander verglichen und bewertet. Dabei werden nicht nur die konventionellen Architekturen Common-Source-LNA und Common-Gate-LNA (CG-LNA) betrachtet, sondern auch alternative Varianten untersucht. Aufgrund der Systemanforderungen wird der CG-LNA als der am besten geeignete ausgewählt. Basierend auf dem EKV-Modell, welches das Verhalten des MOSFETs in allen Arbeitsbereichen beschreibt, wird der CG-LNA analysiert. Dabei werden speziell, die parasitären Kapazitäten des MOSFETs und die durch Kurzkanaleffekte bedingte Zunahme des Rauschens, in Abhängigkeit vom Arbeitspunkt berücksichtigt. In dieser Arbeit konnten weiterhin neue, arbeitspunktabhängige charakteristische Performancekennzahlen (weitenbezogene Source-Transkonduktanz und totale Eingangskapazität sowie Eingangszeitkonstante) des CG-LNAs definiert werden, welche in direkter Verbindung zu der verwendeten Standard-CMOS-Technologie stehen. Mit Hilfe dieser Kenngrößen können die Technologiebedingten Grenzen für den Eingangsreflexionsfaktor und das Noise Figure bestimmt werden. Mit Hilfe einer numerischen Simulation werden die Kennzahlen des CG-LNAs ermittelt. Darauf basierend wird ein Algorithmus formuliert, mittels dessen unter Berücksichtigung der festgelegten Spezifikationen für den LNA (Noise Figure und Eingangsreflexionsfaktor) der optimale Inversionskoeffizient und die dazugehörige Weite bei minimalem Arbeitspunktstrom gefunden werden kann. Die durchgeführte Optimierung zeigt, dass der günstigste Arbeitspunkt im Bereich der moderaten Inversion liegt. Die durch die Optimierung gefundenen Designparameter werden bei der anschließenden schaltungstechnischen Realisierung verwendet und die Kennzahlen des LNAs durch eine Schaltungssimulation verifiziert. Ein weiterer Schwerpunkt dieser Arbeit liegt bei der Erweiterung des entwickelten CG-LNAs um eine variabel einstellbare Verstärkung. Dazu wird ein neues Konzept zur Verstärkungseinstellung vorgestellt und umgesetzt, welches darauf basiert den Arbeitspunktstrom abzusenken. Bei der schaltungstechnischen Umsetzung werden 16 verschiedene Verstärkungsstufen realisiert, wodurch die Verstärkung des LNAs in 1 dB Schritten reduziert werden kann (eine beliebige Stufung ist ebenfalls realisierbar). Der Arbeitspunktstrom wird dabei um fast eine Größenordnung reduziert. Durch Betrachtung des SNR-Ausgangsverhältnisses wird gezeigt, dass bei einer geringeren Verstärkungseinstellung sich keine Verschlechterung des SNR-Verhältnisses im Vergleich zur größten Verstärkungseinstellung ergibt. Der in dieser Arbeit vorgestellte optimierte CG-LNA kann zukünftig in Empfängern mit vergleichbaren Anforderungen eingesetzt werden. Die einstellbare Verstärkung mit gleichzeitig reduzierter Stromaufnahme stellt dabei eine wichtige Entwicklung dar, welche maßgeblich zur Verlängerung der Batterielebensdauer bei mobilen Geräten beiträgt

Analogue circuits for low power communication

Low power electronic circuits are required to extend the operational time of battery operated devices. They are also necessary to reduce the power consumption of equipment in general, especially as the world tries to cut energy usage. The first section of this thesis explores fundamental and implementation limits for low power circuits. The energy requirements of amplification are presented and a lower bound on the energy required to transmit information over a point to point link is proposed. It is evident from the low power limits survey that when a transistor is biased, significant thermodynamic energy is required to reduce the resistance of the channel. A transmitter is presented that turns on a transistor for 0.1 % of transmitted time. This transmitter approximates a Gaussian pulse by allowing the impulse response of two 2nd order transmitting elements to sum in free space. The transmitter is of low complexity and the receiver architecture ensures that no on-line tuning is required. Measured results indicate that by using coherent detection a 1 Mbps, 50 mm distance link with a bit error rate of 10−3 can be achieved. The bandwidth of the transmitted pulse is 30-37.5 MHz and 30 dB of out of band attenuation is provided. An analogue Gabor transform is described which splits a signal into parallel paths of a lower bandwidth. This enables post processing at lower clock rates, which can reduce energy dissipation. An implementation of the transform using sub-threshold CMOS continuous time filters is presented. A novel method for designing low power gmC filters using simple models of identical transconductors is used to specify transistor sizes. Measured results show that the transform consumes 7 μW for an input signal bandwidth of 4 kHz

Design and Linearization of Energy Efficiency Power Amplifier in Nonlinear OFDM Transmitter for LTE-5G Applications. Simulation and measurements of energy efficiency power amplifier in the presence of nonlinear OFDM transmitter system and digital predistortion based on Hammerstein-Wiener method

This research work has made an effort to understand a novel line of radio frequency power amplifiers (RFPAs) that address initiatives for efficiency enhancement and linearity compensation to harmonize the fifth generation (5G) campaign. The objective is to enhance the performance of an orthogonal frequency division multiplexing-long term evolution (OFDM-LTE) transmitter by reducing the nonlinear distortion of the RFPA. The first part of this work explores the design and implementation of 15.5 W class AB RF power amplifier, adopting a balanced technique to stimulate efficiency enhancement and redeeming exhibition of excessive power in the transmitter. Consequently, this work goes beyond improving efficiency over a linear RF power amplifier design; in which a comprehensive investigation on the fundamental and harmonic components of class F RF power amplifier using a load-pull approach to realise an optimum load impedance and the matching network is presented. The frequency bandwidth for both amplifiers was allocated to operate in the 2.620-2.690 GHz of mobile LTE applications. The second part explores the development of the behavioural model for the class AB power amplifier. A particular novel, Hammerstein-Wiener based model is proposed to describe the dynamic nonlinear behaviour of the power amplifier. The RF power amplifier nonlinear distortion is approximated using a new linear parameter approximation approach. The first and second-order Hammerstein-Wiener using the Normalised Least Mean Square Error (NLMSE) algorithm is used with the aim of easing the complexity of filtering process during linear memory cancellation. Moreover, an enhanced adaptive Wiener model is proposed to explore the nonlinear memory effect in the system. The proposed approach is able to balance between convergence speed and high-level accuracy when compared with behavioural modelling algorithms that are more complex in computation. Finally, the adaptive predistorter technique is implemented and verified in the OFDM transceiver test-bed. The results were compared against the computed one from MATLAB simulation for OFDM and 5G modulation transmitters. The results have confirmed the reliability of the model and the effectiveness of the proposed predistorter.Fundacão para a Ciência e a Tecnologia, Portugal, under European Union’s Horizon 2020 research and innovation programme ... grant agreement H2020-MSCA-ITN- 2016 SECRET-722424 I also acknowledge the role of the National Space Research and Development Agency (NASRDA) Sokoto State Government Petroleum Technology Trust Fund (PTDF