A review of technologies and design techniques of millimeter-wave power amplifiers

his article reviews the state-of-the-art millimeter-wave (mm-wave) power amplifiers (PAs), focusing on broadband design techniques. An overview of the main solid-state technologies is provided, including Si, gallium arsenide (GaAs), GaN, and other III-V materials, and both field-effect and bipolar transistors. The most popular broadband design techniques are introduced, before critically comparing through the most relevant design examples found in the scientific literature. Given the wide breadth of applications that are foreseen to exploit the mm-wave spectrum, this contribution will represent a valuable guide for designers who need a single reference before adventuring in the challenging task of the mm-wave PA design

Doctor of Philosophy

dissertationHigh speed wireless communication systems (e.g., long-term evolution (LTE), Wi-Fi) operate with high bandwidth and large peak-to-average power ratios (PAPRs). This is largely due to the use of orthogonal frequency division multiplexing (OFDM) modulation that is prevalent to maximize the spectral efficiency of the communication system. The power amplifier (PA) in the transmitter is the dominant energy consumer in the radio, largely because of the PAPR of the input signal. To reduce the energy consumption of the PA an amplifier that simultaneously achieves high efficiency and high linearity. Furthermore, to lower the cost for high volume production, it is desirable to achieve a complete System-on-Chip (SoC) integration. Linear amplifiers (e.g., Class-A, -B, -AB) are inefficient when amplifying signals with large PAPR that is associated by high peak-to-average modulation techniques such as LTE. OFDM. Switching amplifiers (e.g., Class-D, -E, -F) are very promising due to their high efficiency when compared to their linear amplifier counterparts. Linearization techniques for switching amplifiers have been intensively investigated due to their limited sensitivity to the input amplitude of the signal. Deep-submicron CMOS technology is mostly utilized for logic circuitry, and the Moore's law scaling of CMOS optimizes transistors to operate as high-speed and low-loss switches rather than high gain transistors. Hence, it is advantageous to use transistors in switching mode as switching amplifies and use high-speed digital logic circuitry to implement linearization systems and circuitry. In this work, several linearization architectures are investigated and demonstrated. An envelope elimination and restoration (EER) transmitter that comprises a class-E power amplifier and a 10-bit digital-to-analog converter (DAC) controlled current modulator is investigated. A pipelined switched-capacitor DAC is designed to control an open-loop transconductor that operates as a current modulator, modulating the amplitude of the current supplied to a class-E PA. Such a topology allows for increased filtering of the quantization noise that is problematic in most digital PAs (DPA). The proposed quadrature and multiphase architecture can avoid the bandwidth expansion and delay mismatch associated with polar PAs. The multiphase switched capacitor power amplifier (SCPA) was proposed after the quadrature SCPA and it significantly improves the power efficiency

Fully Integrated 60 GHz Power Amplifiers in 45nm SOI CMOS

With the rapid growth of consumer demand for high data rates and high speed communications, the wireless spectrum has become increasingly precious. This has promoted the evolution of new standards and modulation schemes to improve spectral e fficiency. The allocation of large bandwidths is an alternative to increase the channel capacity and data rate, however the availability of spectrum below 10 GHz is very limited. Recently, the 60 GHz spectrum has emerged as a potential candidate to support multi-Gb/s applications. It off ers 7 GHz of unlicensed spectrum, for development of Wireless Personal Area Networks (WPAN) and cellular backhauls. Meanwhile, the scaling and advancement of low-cost complementary metal-oxide semiconductor (CMOS) technologies has enabled the use of CMOS devices at millimeter wave frequencies and the integration of analogue and digital circuitry has created platform for single chip radio development. However, low power density, low optimum load resistance and poor quality integrated passives (due to lossy silicon substrate) make CMOS technology a poor candidate for power ampli fier (PA) design when, compared to silicon germanium and Group III-V technologies (gallium nitride, gallium arsenide and indium phosphide). In order to overcome the above mentioned challenges in CMOS, this thesis re-explores FET-stacking as a power combining technique at 60 GHz using 45nm silicon-on-insulator (SOI) CMOS for millimeter-wave PAs. The stacking approach enables the use of higher supply voltages to obtain higher output power, and its higher load line resistance Ropt allows for the use of low impedance transformation matching networks. The reliability of CMOS PA under large signal operation is also addressed and improved with the FET-stacking approach applied in this work. This thesis divides the millimeter-wave PA design problem in to two areas, active and passive, both of which are critically designed for optimum performance in terms of effi ciency and output power while taking device and substrate parasitics into consideration. A transistor unit cell combination topology, the 'Manifold', has been analyzed and applied in 45 nm SOI CMOS for large RF power transistor cells. Moreover, various topologies of slow wave coplanar waveguide (CPW) lines are analyzed and implemented on the SOI substrate to synthesize inductors for matching networks at 60 GHz. To demonstrate the active and passive design performance in 45nm SOI CMOS at 60 GHz, a two-stage cascode PA is presented. Measurement under continuous wave (CW) stimulus shows 18.2 dB gain, a 3 dB bandwidth of 20%, 14 dBm saturated output power at 22% peak power-added e fficiency (PAE). Moreover, to validate the FET-stacking analysis, a three-stack PA is designed and fabricated with an output performance of 8.8 dB gain, a 3 dB bandwidth of 20%, 16 dBm saturated output power at 14% peak PAE. Finally, a wideband three stage amplifi er is designed utilizing the two-stage cascode and three-stack PA, achieving 21.5 dB at gain over a fractional bandwidth of 20%, and 16 dBm saturated output power at 13.8% PAE

A linear high-efficiency millimeter-wave CMOS Doherty radiator leveraging on-antenna active load-modulation

This thesis presents a Doherty Radiator architecture that explores multi-feed antennas to achieve an on-antenna Doherty load modulation network and demonstrate high-speed high-efficiency transmission of wideband modulated signals. On the passive circuits, we exploit the multi-feed antenna concept to realize compact and high-efficiency on-antenna active load modulation for close-to-ideal Doherty operation, on-antenna power combining, and mm-Wave signal radiation. Moreover, we analyze the far-field transmission of the proposed Doherty Radiator and demonstrate its wide Field-of-View (FoV). On the active circuits, we employ a GHz-bandwidth adaptive biasing at the Doherty Auxiliary power amplifier (PA) path to enhance the Main/Auxiliary Doherty cooperation and appropriate turning-on/-off of the Auxiliary path. A proof-of-concept Doherty Radiator implemented in a 45nm CMOS SOI process over 62-68GHz exhibits a consistent 1.45-1.53× PAE enhancement at 6dB PBO over an idealistic class-B PA with the same PAE at P1dB. The measured Continuous-Wave (CW) performance at 65GHz demonstrates 19.4/19.2dBm PSAT/P1dB and achieves 27.5%/20.1% PAE at peak/6dB PBO, respectively. For single-carrier 1Gsym/s 64-QAM modulation, the Doherty Radiator shows average output power of 14.2dBm with an average 20.2% PAE and -26.7dB EVM without digital predistortion. Consistent EVMs are observed over the entire antenna FoV, demonstrating spatially undistorted transmission and constant Doherty PBO efficiency enhancement.M.S

A single propagation path multimode CMOS power amplifier based on the stacked topology

Orientador: Bernardo Rego Barros de Almeida LeiteCoorientador: André Augusto MarianoTese (doutorado) - Universidade Federal do Paraná, Setor de Tecnologia, Programa de Pós-Graduação em Engenharia Elétrica. Defesa : Curitiba, 28/06/2021Inclui referências: p. 54-56Resumo: Esta tese apresenta o projeto de um amplificador de potências (PA) prova-de-conceito com quatro perfis de eficiência de um caminho único de propagação, realizado com tecnologia CMOS 130 nm e operando em 2,4 GHz. Esse circuito se baseia em dois conceitos: na seleção da região de operação de transistores (triodo ou saturação) e na alteração da tensão de alimentação de uma arquitetura empilhada modificada. Nos modos de alta e baixa potência (todos transistores em saturação e um transistor em saturação e três em triodo, respectivamente), o ponto de compressão de 1 dB referenciado à saída (OCP1dB) e a eficiência adicionada à potência (PAE) no OCP1dB resultantes de simulação pós-layout são de 19,9 dBm e 25,7%; de 15,1 dBm e 20,5%, respectivamente. Para validar a operação desse PA, quatro tipos de sinais do padrão IEEE 802.11ax foram testados. Para sinais menos complexos (16 QAM) o PA pode operar sem que a ultrapasse os limites impostos pela máscara do padrão até uma potencia de saída (pout) de 17,8 dBm; para sinais mais complexos (1024 QAM) o PA pode operar até uma pout de 8,5 dBm. Por um lado, o circuito apresentado é capaz de ocupar uma pequena área, o que é uma vantagem em processos escaláveis, tais como o CMOS. Por outro lado, a complexidade de design é elevada, tendo em vista que a otimização de eficiência e potência é também função da interação entre os modos de operação.Abstract: This thesis presents the design of a proof-of-concept single propagation path four-mode power amplifier (PA) in 130 nm CMOS operating at 2.4 GHz. It is based on two concepts: the selection of the transistor's operation region (triode or saturation) and on the scaling of supply voltage of a modified stacked architecture. In high and low power modes (all transistors in saturation and one transistor in saturation and three in triode, respectively), the output-referred 1 dB compression point (OCP1dB) and the power added efficiency (PAE) in OCP1dB post-layout simulation results are 19.9 dBm and 25.7%; 15.1 dBm and 20.5%, respectively. To validate this PA's operation capability, four types of IEEE 802.11ax signals were tested. For less complex signals (16 QAM) the PA can operate without exceeding the limits imposed by the standard's mask up to an output power (pout) of 17.8 dBm; for more complex signals (1024 QAM) the PA can operate up to a pout of 8.5 dBm. On the one hand, the proposed circuit is capable of occupying a small area, which is an advantage in scalable processes, such as CMOS is. On the other hand, its design is complex, as optimization of efficiency and power is also a function of the interaction among operation modes

KEY FRONT-END CIRCUITS IN MILLIMETER-WAVE SILICON-BASED WIRELESS TRANSMITTERS FOR PHASED-ARRAY APPLICATIONS

Millimeter-wave (mm-Wave) phased arrays have been widely used in numerous wireless systems to perform beam forming and spatial filtering that can enhance the equivalent isotropically radiated power (EIRP) for the transmitter (TX). Regarding the existing phased-array architectures, an mm-Wave transmitter includes several building blocks to perform the desired delivered power and phases for wireless communication. Power amplifier (PA) is the most important building block. It needs to offer several advantages, e.g., high efficiency, broadband operation and high linearity. With the recent escalation of interest in 5G wireless communication technologies, mm-Wave transceivers at the 5G frequency bands (e.g., 28 GHz, 37 GHz, 39 GHz, and 60 GHz) have become an important topic in both academia and industry. Thus, PA design is a critical obstacle due to the challenges associated with implementing wideband, highly efficient and highly linear PAs at mm-Wave frequencies. In this dissertation, we present several PA design innovations to address the aforementioned challenges. Additionally, phase shifter (PS) also plays a key role in a phased-array system, since it governs the beam forming quality and steering capabilities. A high-performance phase shifter should achieve a low insertion loss, a wide phase shifting range, dense phase shift angles, and good input/output matching.Ph.D

60 GHz transceiver circuits in SiGe-HBT and CMOS technologies

Die Erhöhung der Übertragungsrate von Kommunikationssystemen ist von hohem wissenschaftlichem und wirtschaftlichem Interesse. Die stetige Fortentwicklung dieser Systeme, sowohl unter Aspekten der Hard- als auch der Software, hat ein neues Technologiezeitalter eingeläutet. Verschiedene Szenarien, auf optischen, drahtgebundenen und drahtlosen Technologien basierend, wurden für diese Anwendungen entwickelt. Im 60 GHz ISM-Band (57 GHz bis 65 GHz) ist wegen der hohen Absorptionsverluste bei dieser Frequenz eine Kurzstrecken-Kommunikation mit hoher Datenrate von besonders hohem Interesse. Die Realisierung solcher Systeme erfolgt aufgrund von Kosten- und Massenproduktionsaspekten auf Basis von SiGe-HBT und CMOS Technologien. Schlüsselparameter eines 60 GHz-Transceivers sind eine hohe Ausgangsleistung, niedrige Rauschzahl, geringer Stromverbrauch und niedrige Herstellungskosten. Um den gesamten Frequenzbereich des 60 GHz ISM-Bandes abdecken zu können, wurden zahlreiche Transceivertopologien weltweit diskutiert. Die verfügbare Technologie mit ihren Schlüsselparametern ft, fmax stellt hierbei eine wichtige Randbedingung dar. In dieser Arbeit werden Aspekte des 60 GHz-Transceiver-Designs unter Verwendung einer 0,25 μm SiGe-HBT- und einer 90 nm CMOS-Technologie untersucht. Zunächst wird die Modellierung von passiven und aktiven Komponenten diskutiert. Verschiedene Techniken zur Modellextraktion basierend auf Messungen und elektromagnetischen Simulationen werden gezeigt. Für die wichtigsten passiven Bauelemente werden skalierbare Modelle entwickelt, um das Entwurfsverfahren zu präzisieren. Im nächsten Schritt werden 60 GHz CMOS- und SiGe-HBT- Leistungsverstärker untersucht. Basierend auf diesen Studien wurden zwei HBT und zwei CMOS-Endstufen konzipiert, realisiert und gemessen. Infolge der Verfügbarkeit einer hochgenauen Bauelemente-Bibliothek, ausgereifter Entwurfstechniken und der Verifikation auf Basis von EM-Simulationen konnte an den gemessenen Leistungsverstärkern eine hohe Ausgangsleistung mit guter Effizienz nachgewiesen werden. Die Ergebnisse zeigen weiterhin eine gute Übereinstimmung von Simulationen mit Messungen. Weiterhin wurden auf Basis einer 90 nm CMOS Technologie ein Heterodyne und ein OOK Transceiver entwickelt. Der Heterodyne-Transceiver mit einer Zwischenfrequenz von 20 GHz genügt dabei dem IEEE 802.15.3c Standard und erreicht eine Performance auf Höhe des internationalen Standes von Wissenschaft und Technik. Für den OOK Sender wurde eine neue Topologie entwickelt. Bei diesem Konzept bilden Modulator und Leistungsverstärker eine Einheit, woraus Vorteile hinsichtlich Ausgangsleistung, Effizienz und Chipgröße resultieren. Mit dieser Schaltung wurde in einem Systemtest eine Übertragungsrate von 6 Gbps über eine Entfernung von 4 m erfolgreich nachgewiesen.The rise of high-data-rate hungry applications has brought a new dawn to telecommunication technologies in both hardware and software development aspects. Different scenarios, mainly based on optical, coaxial and wireless systems, have been developed for these multi-gigabit communication systems. In these scenarios, the wireless system is utilized for indoor and short-range communication, which can ease the requirements on RF power and noise figure of the transceivers. However, the demand for multi-gigabit communication imposes a broadband performance requirement upon these wireless transceivers. This broadband performance requirement can be within the range of 2 GHz to 10 GHz. In order to cover such a broad frequency range, different transceiver circuit topologies have been suggested by many circuit designers. Due to the high oxygen loss in the 60 GHz range this 57 GHz to 65 GHz ISM band has attracted attention for high speed short-range communication. Moreover, the newly emerged low cost technologies (like, CMOS and SiGe HBT) have further attracted the industry to explore this communication band. The main requirements for a 60 GHz transceiver are high output power, low noise figure, low power consumption and broadband performance. To cover the whole 57 GHz to 65 GHz frequency band, numerous transceiver topologies are under discussion. The key parameter ft, fmax of the available technology define the achievable system performance. In this thesis, multiple aspects of the 60 GHz transceiver design based on the 90 nm CMOS and 0.25 μm SiGe HBT designs have been investigated. First, the modeling of passive and active components is presented. These components include capacitors, inductors, transformers, transmission lines, transistors, matching networks and RF pads. Different techniques for model extraction based on measurements and electromagnetic simulations have been examined. For inductors, transformers and capacitors scalable models have been developed. Further, the design techniques of 60 GHz CMOS and SiGe HBT power amplifiers have been studied. Based on these studies, two HBT and two CMOS power amplifiers have been designed, realized and measured. Due to accurate modeling and design techniques, high performance and good agreement with simulation has been achieved. Finally, two different types of transmitters (Heterodyne and OOK) based on the CMOS technology have been developed. The heterodyne transceiver, with an IF frequency of around 20 GHz, has been designed based on the IEEE 802.15.3c standard. This transmitter has achieved state of the art results with respect to output power, conversion gain and efficiency with a small chip size and low power consumption. For the OOK transmitter, a novel topology has been developed. In this topology, the modulator and the power amplifier have been integrated into one circuit. Due to many advantages of this new topology, this transmitter achieves higher output power and efficiency compared with state-of-the-art results. Furthermore, the realized circuit has been utilized within a wireless system where more than 6 Gbps has been successfully transmitted over a 4 m distance

Radio Frequency and Millimeter Wave Circuit Component Design with SiGe BiCMOS Technology

The objective of this research is to study and leverage the unique properties and advantages of silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) integrated circuit technologies to better design radio frequency (RF) and millimeter wave (mm-wave) circuit components. With recent developments, the high yield and modest cost silicon-based semiconductor technologies have proven to be attractive and cost-effective alternatives to high-performance III-V technology platforms. Between SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology and advanced RF complementary metal-oxide-semiconductor (CMOS) technology, the fundamental device-level differences between SiGe HBTs and field-effect transistors (FETs) grant SiGe HBTs clear advantages as well as unique design concerns. The work presented in this dissertation identifies several advantages and challenges on design using SiGe HBTs and provides design examples that exploit and address these unique benefits and problems with circuit component designs using SiGe HBTs.Ph.D

Digital Radio Encoding and Power Amplifier Design for Multimode and Multiband Wireless Communications

The evolution of wireless technology has necessitated the support of multiple communication standards by mobile devices. At present, multiple chipsets/radios operating at predefined sets of modulation schemes, frequency bands, bandwidths and output power levels are used to achieve this objective. This leads to higher component counts, increased cost and limits the capacity to cope with future communication standards. In order to tackle different wireless standards using a single chipset, digital circuits have been increasingly deployed in radios and demonstrated re-configurability in different modulation schemes (multimode) and frequency bands (multiband). Despite efforts and progress made in digitizing the entire radio, the power amplifier (PA) is still designed using an conventional approach and has become the bottleneck in digital transmitters, in terms of low average power efficiency, poor compatibility with modern CMOS technology and limited re-configurability. This research addresses these issues from two aspects. The first half of the thesis investigates signal encoding issues between the modulator and PA. We propose, analyze and evaluate a new hybrid amplitude/time signal encoding scheme that significantly improves the coding efficiency and dynamic range of a digitally modulated power amplifier (DMPA) without significantly increasing design complexity. The proposed hybrid amplitude/time encoding scheme combines both the amplitude domain and the time domain to optimally encode information. Experimental results show that hybrid amplitude/time encoding results in a 35% increase in the average coding efficiency with respect to conventional time encoding, and is only 6.7% lower than peak efficiency when applied to a Wireless Local Area Network (WLAN) signal with a peak to average power ratio equal to 9.9 dB. A new DMPA architecture, based on the proposed hybrid encoding, is also proposed. The second half of this thesis presents the design, analysis and implementation of a CMOS PA that is amenable to the proposed hybrid encoding scheme. A multi-way current mode class-D PA architecture has been proposed and realized in 130 nm CMOS technology. The designed PA has satisfied the objectives of wide bandwidth (1.5 GHz - 2.7 GHz at 1 dB output power), and high efficiency (PAE 63%) in addition to demonstrating linear responses using the proposed digital encoding. A complete digital transmitter combining the encoder and the multi-way PA was also investigated. The overall efficiency is 27% modulating 7.3 dB peak to average power ratio QAM signals