Digital enhancement techniques for fractional-N frequency synthesizers

Meeting the demand for unprecedented connectivity in the era of internet-of-things (IoT) requires extremely energy efficient operation of IoT nodes to extend battery life. Managing the data traffic generated by trillions of such nodes also puts severe energy constraints on the data centers. Clock generators that are essential elements in these systems consume significant power and therefore must be optimized for low power and high performance. The focus of this thesis is on improving the energy efficiency of frequency synthesizers and clocking modules by exploring design techniques at both the architectural and circuit levels. In the first part of this work, a digital fractional-N phase locked loop (FNPLL) that employs a high resolution time-to-digital converter (TDC) and a truly ΔΣ fractional divider to achieve low in-band noise with a wide bandwidth is presented. The fractional divider employs a digital-to-time converter (DTC) to cancel out ΔΣ quantization noise in time domain, thus alleviating TDC dynamic range requirements. The proposed digital architecture adopts a narrow range low-power time-amplifier based TDC (TA-TDC) to achieve sub 1ps resolution. Fabricated in 65nm CMOS process, the prototype PLL achieves better than -106dBc/Hz in-band noise and 3MHz PLL bandwidth at 4.5GHz output frequency using 50MHz reference. The PLL achieves excellent jitter performance of 490fsrms, while consumes only 3.7mW. This translates to the best reported jitter-power figure-of-merit (FoM) of -240.5dB among previously reported FNPLLs. Phase noise performance of ring oscillator based digital FNPLLs is severely compromised by conflicting bandwidth requirements to simultaneously suppress oscillator phase and quantization noise introduced by the TDC, ΔΣ fractional divider, and digital-to-analog converter (DAC). As a consequence, their FoM that quantifies the power-jitter tradeoff is at least 25dB worse than their LC-oscillator based FNPLL counterparts. In the second part of this thesis, we seek to close this performance gap by extending PLL bandwidth using quantization noise cancellation techniques and by employing a dual-path digital loop filter to suppress the detrimental impact of DAC quantization noise. A prototype was implemented in a 65nm CMOS process operating over a wide frequency range of 2.0GHz-5.5GHz using a modified extended range multi-modulus divider with seamless switching. The proposed digital FNPLL achieves 1.9psrms integrated jitter while consuming only 4mW at 5GHz output. The measured in-band phase noise is better than -96 dBc/Hz at 1MHz offset. The proposed FNPLL achieves wide bandwidth up to 6MHz using a 50 MHz reference and its FoM is -228.5dB, which is at about 20dB better than previously reported ring-based digital FNPLLs. In the third part, we propose a new multi-output clock generator architecture using open loop fractional dividers for system-on-chip (SoC) platforms. Modern multi-core processors use per core clocking, where each core runs at its own speed. The core frequency can be changed dynamically to optimize for performance or power dissipation using a dynamic frequency scaling (DFS) technique. Fast frequency switching is highly desirable as long as it does not interrupt code execution; therefore it requires smooth frequency transitions with no undershoots. The second main requirement in processor clocking is the capability of spread spectrum frequency modulation. By spreading the clock energy across a wide bandwidth, the electromagnetic interference (EMI) is dramatically reduced. A conventional PLL clock generation approach suffers from a slow frequency settling and limited spread spectrum modulation capabilities. The proposed open loop fractional divider architecture overcomes the bandwidth limitation in fractional-N PLLs. The fractional divider switches the output frequency instantaneously and provides an excellent spread spectrum performance, where precise and programmable modulation depth and frequency can be applied to satisfy different EMI requirements. The fractional divider has unlimited modulation bandwidth resulting in spread spectrum modulation with no filtering, unlike fractional-N PLL; consequently it achieves higher EMI reduction. A prototype fractional divider was implemented in a 65nm CMOS process, where the measured peak-to-peak jitter is less than 27ps over a wide frequency range from 20MHz to 1GHz. The total power consumption is about 3.2mW for 1GHz output frequency. The all-digital implementation of the divider occupies the smallest area of 0.017mm2 compared to state-of-the-art designs. As the data rate of serial links goes higher, the jitter requirements of the clock generator become more stringent. Improving the jitter performance of conventional PLLs to less than (200fsrms) always comes with a large power penalty (tens of mWs). This is due to the PLL coupled noise bandwidth trade-off, which imposes stringent noise requirements on the oscillator and/or loop components. Alternatively, an injection-locked clock multiplier (ILCM) provides many advantages in terms of phase noise, power, and area compared to classical PLLs, but they suffer from a narrow lock-in range and a high sensitivity to PVT variations especially at a large multiplication factor (N). In the fourth part of this thesis, a low-jitter, low-power LC-based ILCM with a digital frequency-tracking loop (FTL) is presented. The proposed FTL relies on a new pulse gating technique to continuously tune the oscillator's free-running frequency. The FTL ensures robust operation across PVT variations and resolves the race condition existing in injection locked PLLs by decoupling frequency tuning from the injection path. As a result, the phase locking condition is only determined by the injection path. This work also introduces an accurate theoretical large-signal analysis for phase domain response (PDR) of injection locked oscillators (ILOs). The proposed PDR analysis captures the asymmetric nature of ILO's lock-in range, and the impact of frequency error on injection strength and phase noise performance. The proposed architecture and analysis are demonstrated by a prototype fabricated in 65 nm CMOS process with active area of 0.25mm2. The prototype ILCM multiplies the reference frequency by 64 to generate an output clock in the range of 6.75GHz-8.25GHz. A superior jitter performance of 190fsrms is achieved, while consuming only 2.25mW power. This translates to a best FoM of -251dB. Unlike conventional PLLs, ILCMs have been fundamentally limited to only integer-N operation and cannot synthesize fractional-N frequencies. In the last part of this thesis, we extend the merits of ILCMs to fractional-N and overcome this fundamental limitation. We employ DTC-based QNC techniques in order to align injected pulses to the oscillator's zero crossings, which enables it to pull the oscillator toward phase lock, thus realizing a fractional-N ILCM. Fabricated in 65nm CMOS process, a prototype 20-bit fractional-N ILCM with an output range of 6.75GHz-8.25GHz consumes only 3.25mW. It achieves excellent jitter performance of 110fsrms and 175fsrms in integer- and fractional-N modes respectively, which translates to the best-reported FoM in both integer- (-255dB) and fractional-N (-252dB) modes. The proposed fractional-N ILCM also features the first-reported rapid on/off capability, where the transient absolute jitter performance at wake-up is bounded below 4ps after less than 4ns. This demonstrates almost instantaneous phase settling. This unique capability enables tremendous energy saving by turning on the clock multiplier only when needed. This energy proportional operation leverages idle times to save power at the system-level of wireline and wireless transceivers

Hybrid apparatus for Bose-Einstein condensation and cavity quantum electrodynamics: Single atom detection in quantum degenerate gases

We present and characterize an experimental system in which we achieve the integration of an ultrahigh finesse optical cavity with a Bose-Einstein condensate (BEC). The conceptually novel design of the apparatus for the production of BECs features nested vacuum chambers and an in-vacuo magnetic transport configuration. It grants large scale spatial access to the BEC for samples and probes via a modular and exchangeable "science platform". We are able to produce \87Rb condensates of five million atoms and to output couple continuous atom lasers. The cavity is mounted on the science platform on top of a vibration isolation system. The optical cavity works in the strong coupling regime of cavity quantum electrodynamics and serves as a quantum optical detector for single atoms. This system enables us to study atom optics on a single particle level and to further develop the field of quantum atom optics. We describe the technological modules and the operation of the combined BEC cavity apparatus. Its performance is characterized by single atom detection measurements for thermal and quantum degenerate atomic beams. The atom laser provides a fast and controllable supply of atoms coupling with the cavity mode and allows for an efficient study of atom field interactions in the strong coupling regime. Moreover, the high detection efficiency for quantum degenerate atoms distinguishes the cavity as a sensitive and weakly invasive probe for cold atomic clouds

Ultra-High Frequency Nanoelectromechanical Systems with Low-Noise Technologies for Single-Molecule Mass Sensing

Advancing today's very rudimentary nanodevices toward functional nanosystems with considerable complexity and advanced performance imposes enormous challenges. This thesis presents the research on ultra-high frequency (UHF) nanoelectromechanical systems (NEMS) in combination with low-noise technologies that enable single-molecule mass sensing and offer promises for NEMS-based mass spectrometry (MS) with single-Dalton sensitivity. The generic protocol for NEMS resonant mass sensing is based on real-time locking and tracking of the resonance frequency as it is shifted by the mass-loading effect. This has been implemented in two modes: (i) creating an active self-sustaining oscillator based on the NEMS resonator, and (ii) a higher-precision external oscillator phase-locking to and tracking the NEMS resonance. The first UHF low-noise self-sustaining NEMS oscillator has been demonstrated by using a 428MHz vibrating NEMS resonator as the frequency reference. This stable UHF NEMS oscillator exhibits ~0.3ppm frequency stability and ~50zg (1zg = 10-21 g) mass resolution with its excellent wideband-operation (~0.2MHz) capability. Given its promising phase noise performance, the active NEMS oscillator technology also offers important potentials for realizing NEMS-based radio-frequency (RF) local oscillators, voltage-controlled oscillators (VCOs), and synchronized oscillators and arrays that could lead to nanomechanical signal processing and communication. The demonstrated NEMS oscillator operates at much higher frequency than conventional crystal oscillators and their overtones do, which opens new possibilities for the ultimate miniaturization of advanced crystal oscillators. Low-noise phase-locked loop (PLL) techniques have been developed and engineered to integrate with the resonance detection circuitry for the passive UHF NEMS resonators. Implementations of the NEMS-PLL mode with generations of low-loss UHF NEMS resonators demonstrate improving performance, namely, reduced noise and enhanced dynamic range. Very compelling frequency stability of ~0.02ppm and unprecedented mass sensitivity approaching 1zg has been achieved with a typical 500MHz device in the narrow-band NEMS-PLL operation. Retaining high quality factors (Q's) while scaling up frequency has become crucial for UHF NEMS resonators. Extensive measurements, together with theoretical modeling, have been performed to investigate various energy loss mechanisms and their effects on UHF devices. This leads to important insights and guidelines for device Q-engineering. The first VHF/UHF silicon nanowire (NW) resonators have been demonstrated based on single-crystal Si NWs made by bottom-up chemical synthesis nanofabrication. Pristine Si NWs have well-faceted surfaces and exhibit high Q's (Q ≈ 13100 at 80MHz and Q ≈ 5750 at 215MHz). Given their ultra-small active mass and very high mass responsivity, these Si NWs also offer excellent mass sensitivity in the ~10?50zg range. These UHF NEMS and electronic control technologies have demonstrated promising mass sensitivity for kilo-Dalton-range single-biomolecule mass sensing. The achieved performance roadmap, and that extended by next generations of devices, clearly indicates realistic and viable paths toward the single-Dalton mass sensitivity. With further elaborate engineering, prototype NEMS-MS is optimistically within reach.</p

A Bose-condensed, simultaneous dual-species Mach-Zehnder atom interferometer

This paper presents the first realization of a simultaneous 87Rb-85Rb Mach-Zehnder atom interferometer with Bose-condensed atoms. A number of ambitious proposals for precise terrestrial and space based tests of the weak equivalence principle rely on suc

Ultra-wideband CMOS signal generator using tunable linear superposition

Department of Electrical EngineeringWireless communication frequency bandwidth and center frequency are have been widening for high speed transmission of data. But the frequency bandwidth a transceiver can cover is severely limited. The circuit designed in the paper, called "signal generator", can offer a variety of wireless bandwidths. In this paper, a ultra wideband signal generator, based in 65nm CMOS technology, is designed after proposing and verifying two different types of signal generator design. The first version design of the signal generator is proposed, which is composed of a four-stage LC-ring voltagecontrolled oscillator (VCO) and a frequency synthesis circuit. A new concept of tunable linear superposition is proposed for wideband frequency synthesis and implemented to provide VCO core (1X)/ twofold (2X)/ quadruple (4X) programmable frequency multiplication function. In order to expand frequency coverage further, the LCring VCO adopted the tunable inductors which are composed of switchable bondwire pairs. A ultra-wideband operation from 4.3GHz to 27.4GHz was experimentally verified. The second version design of the signal generator using a reconfigurable phase selection process is proposed, which is proposed and consists of a multi-phase signal generation and a programmable frequency multiplication. This chip is proposed for wideband frequency synthesis and implemented to provide VCO core (1X)/ twofold (2X)/ quadruple (4X) and octuplet (8X) programmable frequency multiplication function. An LC-ring oscillator and a selective rectifying combiner are reconstructed adaptively for various frequency synthesis modes, minimizing their power consumption. A fully-integrated prototype verified to have very wide frequency characteristic from 6.3GHz to 59.4GHz.ope

Q-switched diode lasers

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