Digital Controlled Multi-phase Buck Converter with Accurate Voltage and Current Control

abstract: A 4-phase, quasi-current-mode hysteretic buck converter with digital frequency synchronization, online comparator offset-calibration and digital current sharing control is presented. The switching frequency of the hysteretic converter is digitally synchronized to the input clock reference with less than ±1.5% error in the switching frequency range of 3-9.5MHz. The online offset calibration cancels the input-referred offset of the hysteretic comparator and enables ±1.1% voltage regulation accuracy. Maximum current-sharing error of ±3.6% is achieved by a duty-cycle-calibrated delay line based PWM generator, without affecting the phase synchronization timing sequence. In light load conditions, individual converter phases can be disabled, and the final stage power converter output stage is segmented for high efficiency. The DC-DC converter achieves 93% peak efficiency for Vi = 2V and Vo = 1.6V.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Small Form Factor Hybrid CMOS/GaN Buck Converters for 10W Point of Load Applications

abstract: Point of Load (PoL) converters are important components to the power distribution system in computer power supplies as well as automotive, space, nuclear, and medical electronics. These converters often require high output current capability, low form factor, and high conversion ratios (step-down) without sacrificing converter efficiency. This work presents hybrid silicon/gallium nitride (CMOS/GaN) power converter architectures as a solution for high-current, small form-factor PoL converters. The presented topologies use discrete GaN power devices and CMOS integrated drivers and controller loop. The presented power converters operate in the tens of MHz range to reduce the form factor by reducing the size of the off-chip passive inductor and capacitor. Higher conversion ratio is achieved through a fast control loop and the use of GaN power devices that exhibit low parasitic gate capacitance and minimize pulse swallowing. This work compares three discrete buck power converter architectures: single-stage, multi-phase with 2 phases, and stacked-interleaved, using components-off-the-shelf (COTS). Each of the implemented power converters achieves over 80% peak efficiency with switching speeds up-to 10MHz for high conversion ratio from 24V input to 5V output and maximum load current of 10A. The performance of the three architectures is compared in open loop and closed loop configurations with respect to efficiency, output voltage ripple, and power stage form factor. Additionally, this work presents an integrated CMOS gate driver solution in CMOS 0.35um technology. The CMOS integrated circuit (IC) includes the gate driver and the closed loop controller for directly driving a single-stage GaN architecture. The designed IC efficiently drives the GaN devices up to 20MHz switching speeds. The presented controller technique uses voltage mode control with an innovative cascode driver architecture to allow a 3.3V CMOS devices to effectively drive GaN devices that require 5V gate signal swing. Furthermore, the designed power converter is expected to operate under 400MRad of total dose, thus enabling its use in high-radiation environments for the large hadron collider at CERN and nuclear facilities.Dissertation/ThesisMasters Thesis Electrical Engineering 201

Multifrequency Averaging in Power Electronic Systems

Power electronic systems have been widely used in the electrical power processing for applications with power levels ranging from less than one watt in battery-operated portable devices to more than megawatts in the converters, inverters and rectifiers of the utility power systems. These systems typically involve the passive elements such as inductors, capacitors, and resistors, the switching electronic components such as IGBTs, MOSFETS, and diodes, and other electronic circuits. Multifrequency averaging is one of the widely used modeling and simulation techniques today for the analysis and design of power electronic systems. This technique is capable of providing the average behavior as well as the ripple behavior of power electronic systems. This work begins with the extension of multifrequency averaging to represent uniformly sampled PWM converters. A new multifrequency averaging method of solving an observed issue with model stability is proposed and validated. Multifrequency averaging can also be applied to study the instability phenomenon in power electronic systems. In particular, a reduced-order multifrequency averaging method, along with a genetic algorithm based procedure, is proposed in this work to estimate the regions of attraction of power electronic converters. The performance of this method is shown by comparing the accuracy and efficiency with the existing methods. Finally, a new continuous-time multifrequency averaging method of representing discrete-time systems is proposed. The proposed method is applied to model digitally controlled PWM converters. Simulation and hardware results show that the proposed method is capable of predicting the average behavior as well as the ripple behavior of the closed-loop systems. Future research in the area of multifrequency averaging is proposed

Low Power DC-DC Converters and a Low Quiescent Power High PSRR Class-D Audio Amplifier

High-performance DC-DC voltage converters and high-efficient class-D audio amplifiers are required to extend battery life and reduce cost in portable electronics. This dissertation focuses on new system architectures and design techniques to reduce area and minimize quiescent power while achieving high performance. Experimental results from prototype circuits to verify theory are shown. Firstly, basics on low drop-out (LDO) voltage regulators are provided. Demand for system-on-chip solutions has increased the interest in LDO voltage regulators that do not require a bulky off-chip capacitor to achieve stability, also called capacitor- less LDO (CL-LDO) regulators. Several architectures have been proposed; however, comparing these reported architectures proves difficult, as each has a distinct process technology and specifications. This dissertation compares CL-LDOs in a unified manner. Five CL-LDO regulator topologies were designed, fabricated, and tested under common design conditions. Secondly, fundamentals on DC-DC buck converters are presented and area reduction techniques for the external output filter, power stage, and compensator are proposed. A fully integrated buck converter using standard CMOS technology is presented. The external output filter has been fully-integrated by increasing the switching frequency up to 45 MHz. Moreover, a monolithic single-input dual-output buck converter is proposed. This architecture implements only three switches instead of the four switches used in conventional solutions, thus potentially reducing area in the power stage through proper design of the power switches. Lastly, a monolithic PWM voltage mode buck converter with compact Type-III compensation is proposed. This compensation scheme employs a combination of Gm-RC and Active-RC techniques to reduce the area of the compensator, while maintaining low quiescent power consumption and fast transient response. The proposed compensator reduces area by more than 45% when compared to an equivalent conventional Type-III compensator. Finally, basics on class-D audio amplifiers are presented and a clock-free current controlled class-D audio amplifier using integral sliding mode control is proposed. The proposed amplifier achieves up to 82 dB of power supply rejection ratio and a total harmonic distortion plus noise as low as 0.02%. The IC prototype’s controller consumes 30% less power than those featured in recently published works

Reducing Power Loss, Cost and Complexity of SoC Power Delivery Using Integrated 3-Level Voltage Regulators

Traditional methods of system-on-chip (SoC) power management based on dynamic voltage and frequency scaling (DVFS) is limited by 1) cores/IP blocks sharing a voltage domain provided by off-chip voltage regulators (VR) and 2) slow voltage scaling time $(<0.1V/\mu s)$. This global, slow DVFS cannot track the increasingly heterogeneous, fluctuating performance requirements of individual microprocessor cores and SoC components. Furthermore, traditional off-chip VRs add significant area overhead and component cost on the board. This thesis explores replacing a large portion of existing off-chip VRs with integrated voltage regulators (IVR) that can scale the voltage at a 50 mV/ns rate, which is 500 times faster than microsecond-scale voltage scaling with existing off-chip VRs. IVRs occupy 10 times smaller footprint than off-chip VRs, making it easy to duplicate them to provide per-core or per-IP-block voltage control. This thesis starts by summarizing the benefits of using IVRs to deliver power to SoCs. Based on a simulation study targeting a 1.6W, 4-core SoC, I show that greater than 20% energy savings is possible with fast, per-core DVFS enabled by IVRs. Next, I present two stand-alone IVR test-chips converting 1.8V and 2.4V to 0.4-1.4V while delivering maximum 1W to the output. Both test-chips incorporate a 3-level VR topology, which is suitable for integration because the topology allows for much smaller inductors (1nH) than existing inductor-based buck VRs. I also discuss reasons behind lower-than-simulated efficiencies in the test-chips and ways to improve. Finally, I conclude with future process technologies that can boost IVR conversion efficiencies and power densities.Engineering and Applied Science

Design and Control of Power Converters 2019

In this book, 20 papers focused on different fields of power electronics are gathered. Approximately half of the papers are focused on different control issues and techniques, ranging from the computer-aided design of digital compensators to more specific approaches such as fuzzy or sliding control techniques. The rest of the papers are focused on the design of novel topologies. The fields in which these controls and topologies are applied are varied: MMCs, photovoltaic systems, supercapacitors and traction systems, LEDs, wireless power transfer, etc

Efficiency Optimization in Digitally Controlled Flyback DC-DC Converters Over Wide Ranges of Operating Conditions

Because of increasingly demanding energy programs and initiatives, it is required to maintain high efficiency in various DC-DC converter applications over wide ranges of operating conditions. To achieve these efficiency goals, this thesis introduces an efficiency optimization approach, which can be applied to given power stages. In the proposed optimization approach, power stage design parameters and controller parameters are concurrently optimized over a range of operating conditions based on power loss models and multi-variable non-linear constrained optimization. A digital controller facilitates on-line efficiency optimization by storing the optimum controller parameters in a look-up table. A flyback DC-DC converter, commonly used in low output power applications, is adopted for experimental verifications of the proposed optimization approach. A valley switching technique is employed to significantly decrease MOSFET turn-on switching loss in discontinuous conduction mode (DCM), and solutions to a problem related to undesirable frequency hopping, commonly observed in other valley switching schemes, are proposed and discussed. A gain-scheduled compensator and a new control scheme, named k-control, are implemented for consistent transient responses over different operating conditions. Finally, simplified sensing and analog-to-digital (A/D) conversion techniques are proposed, targeting a low-cost, small-size and low-pin-count (≤ 8) digital controller IC chip implementation

Architectures and circuits for low-voltage energy conversion and applications in renewable energy and power management

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.Includes bibliographical references (p. 337-343).In this thesis we seek to develop smaller, less expensive, and more efficient power electronics. We also investigate emerging applications where the proper implementation of these new types of power converters can have a significant impact on the overall system performance. We have developed a new two-stage dc-dc converter architecture suitable for low-voltage CMOS power delivery. The architecture, which combines the benefits of switched-capacitor and inductor-based converters, achieves both large voltage step-down and high switching frequency, while maintaining good efficiency. We explore the benefits of a new soft-charging technique that drastically reduces the major loss mechanism in switched-capacitor converters, and we show experimental results from a 5-to-1 V, 0.8 W integrated dc-dc converter developed in 180 nm CMOS technology. The use of power electronics to increase system performance in a portable thermophotovoltaic power generator is also investigated in this thesis. We show that mechanical non-idealities in a MEMS fabricated energy conversion device can be mitigated with the help of low-voltage distributed maximum power point tracking (MPPT) dc-dc converters. As part of this work, we explore low power control and sensing architectures, and present experimental results of a 300 mW integrated MPPT developed in 0.35 um CMOS with all power, sensing and control circuitry on chip. The final piece of this thesis investigates the implementation of distributed power electronics in solar photovoltaic applications. We explore the benefits of small, intelligent power converters integrated directly into the solar panel junction box to enhance overall energy capture in real-world scenarios. To this end, we developed a low-cost, high efficiency (>98%) power converter that enables intelligent control and energy conversion at the sub-panel level. Experimental field measurements show that the solution can provide up to a 35% increase in panel output power during partial shading conditions compared to current state-of-the-art solutions.by Robert C. N. Pilawa-Podgurski.Ph.D