123 research outputs found

    RF Front End for an Integrated Silhouette Capture and Boundary Detection Frequency Modulated Continuous Wave Ultra-Wideband Radar System for the Extension of Independent Living

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    Limitations of current eldercare monitoring systems leave a need for new solutions. A monitoring system based on a frequency modulated continuous wave ultra-wideband short-range radar is proposed for this application. The complete proposed monitoring system is comprised of four blocks: boundary detection, silhouette capture, human identification, and data transmission. This paper develops the RF front end hardware for the silhouette capture subsystem. System requirements are derived for the silhouette capture subsystem. An architecture for the RF front end is designed, and required individual component specifications are determined. Components are selected off the shelf or custom designed for each socket. Full transmitter and receiver level plans are calculated to ensure expected system performance meets system requirements. A component library and full system schematic is created, PCB layout is completed, and PCB files are generated and sent for fabrication. PCB traces and individual components are characterized over frequency, and methods that improve inadequate performance are documented and discussed

    A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

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    © 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio

    A Software-Defined Radio Receiver in 65nm CMOS Robust to Out-of-Band Interference

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    Two techniques are presented in this paper for a software-defined radio (SDR) receiver robust to out-of-band interference. Voltage gain is realized at IF simultaneously with low-pass filtering to mitigate blockers and out-of-band intermodulation distortion. A 2-stage polyphase harmonic rejection (HR) mixer concept robust to gain error achieves 2nd-6th HR of more than 60dB for 40 samples without trimming or calibration. A prototype 0.4-0.9G zero-IF receiver in 65nm CMOS has 34dB gain, 4dB NF, +3.5dBm IIP3 and +47dBm IIP2 while drawing 50mA from 1.2V

    Digitally-Assisted RF IC Design Techniques for Reliable Performance

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    Semiconductor industries have competitively scaled down CMOS devices to attain benefits of low cost, high performance, and high integration density in digital integrated circuits. On the other hand, deep scaled technologies inextricably accompany a large process variation, supply voltage scaling, and reduction in breakdown voltages of transistors. When it comes to RF/analog IC design, CMOS scaling adversely affects its reliability due to large performance variation and limited linearity. For addressing the issues related to variations and linearity, this research proposes the following digitally-assisted RF circuit design techniques: self-calibration system for RF phase shifters and wide dynamic range LNAs. Due to PVT variations in scaled technologies, RF phase shifter design becomes more challenging with device scaling. In the proposed self-calibration topology, we devised a novel phase sensing method and a pulsewidth-to-digital converter. The feedback controller is also designed in digital domain, which is robust to PVT variations. These unique techniques enable a sensing/control loop tolerant to PVT variations. The self-calibration loop was applied to a 7 to 13GHz phase shifter. With the calibration, the estimated phase error is less than 2 degrees. To overcome the linearity issue in scaled technologies, a digitally-controlled dual-mode LNA design is presented. A narrowband (5.1GHz) and a wideband (0.8 to 6GHz) LNA can be toggled between high-gain and high-linearity modes by digital control bits according to the input signal power. A compact design, which provides negligible performance degradation by additional circuitry, is achieved by sharing most of the components between the two operation modes. The narrowband and the wideband LNA achieves an input-referred P1dB of -1.8dBm and +4.2dBm, respectively

    A Low-Cost Ultra-Wideband Test-Bed

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    This paper presents the design and implementation of a simple transceiver test-bed for implementing and testing algorithms for impulsive UWB applications. The platform has been developed using low-cost off-the-shelf components. We have conceived a simple modular architecture that was targeted to low power, short-range applications. The test-bed is discussed,commenting on the main design decisions and the benefits of the chosen architecture. Measurements of some blocks of the system are also presented.Fil: Altieri, Andrés Oscar. Consejo Nacional de Investigaciones Científicas y Técnicas. Oficina de Coordinación Administrativa Parque Centenario. Centro de Simulación Computacional para Aplicaciones Tecnológicas; ArgentinaFil: Gámez, Pablo. Instituto Nacional de Tecnología Industrial; ArgentinaFil: Marchi, Edgardo Jose. Instituto Nacional de Tecnología Industrial; ArgentinaFil: Cervetto, Marcos. Instituto Nacional de Tecnología Industrial; ArgentinaFil: Bouza, Magadalena. Universidad de Buenos Aires. Facultad de Ingeniería. Departamento de Electronica; ArgentinaFil: Galarza, Cecilia Gabriela. Consejo Nacional de Investigaciones Científicas y Técnicas. Oficina de Coordinación Administrativa Parque Centenario. Centro de Simulación Computacional para Aplicaciones Tecnológicas; ArgentinaXXXV Simpósio Brasileiro de Telecomunicações e Processamento de SinaisSan PedroBrasilSociedade Brasileira de Telecomunicaçõe

    Design and Optimization of a Direct-Conversion Double-Balanced Mixer for RF Receiver Front-End

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    Differential implementation is becoming highly favoured in RFIC (radio frequency integrated circuit) design, notably its high immunity to common-mode noises, acceptable rejection of parasitic coupling, and increased dynamic range. One specific RF front-end building block that is usually designed as a differential circuit is the mixer.  This technical paper presents a study of a differential mixer, notably the double-balanced mixer implemented on a direct-conversion architecture in a standard 90nm CMOS (complementary metal-oxide semiconductor) process.  Operating frequency is set at 5GHz, which is a typical frequency for RF (radio frequency) receiver.   Impedance matching was essential to fully optimize the mixer design.  The direct-conversion double-balance mixer design eventually achieved conversion gain of 11.463dB and noise figure of 16.529dB, comparable to mixer designs from past research and studies

    High Resolution/Wideband on-Chip Phase-Shifting

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    A new active LO phase shifter was introduced and implemented in a 2x2 wide band MIMO receiver. The chip was designed with STMicroelectronics 90nm technology. The main advantages of the proposed phase shifter over previous works included a wide band range, high resolution and small area. The phase shifter is based on the dependency of the inverter propagation delay on the load capacitance. Simply, by changing the load capacitance of an inverter, a different propagation delay is generated. A number of these controllable delay cells are cascaded to provide the required phase-shift. In order for the delay cells to reduce the required amount of phase-shifting the I&Q swap circuit is introduced. The I&Q swap circuitry reduces the phase-shifting by one fourth of the original range. The wide band phase shifter is suitable for multi-standard radios, since just one phase shifter is needed to support all standards. This capability of the phase shifter could potentially reduce the size of the die and simplify the design. The measurement shows that the phase shifter is able to provide 360˚ of phase-shifting at the output base band signal when the LO is varying from 1.5GHz to 6GHz. A wider range of the phase shifter is achievable by reducing the capacitance load and increasing the number of cascaded delay cells. The proposed phase shifter is capable of achieving a very high resolution. The resolution of the phase shifter is a function of the inverter current capability and the load capacitance. The measurements show the average resolution of the proposed phase shifter is about 1.32ps. Passive components usually take up a large area on the chip. A MOS capacitor is used as the load to reduce the area of the proposed phase shifter. A method is proposed to improve the phase shifter stability over the temperature and process variations. This method is based on the fact that the propagation delay of an inverter is inversely proportional to the power supply. Therefore, the phase shifters’ power supply must be varied to maintain a relatively constant phase shifter resolution over the temperature and process variations

    Design of a Built-In Test Equipment for a X-band phased array radar system in SiGe BiCMOS technology

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    In this work an X band Build In Test Equipment (BITE), implemented in the SiGe BiCMOS technology of Infineon, is presented. The possibility to perform precise measurements of phase shift and gain in the X- band, using lower frequency ( 4GHz-6GHz) automated test equipment (ATE), which is also used in WLAN devices, is investigated, leading to the design of the complete test equipment and finally to the full custom layout desig
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