An agile supply modulator with improved transient performance for power efficient linear amplifier employing envelope tracking techniques

This article presents an agile supply modulator with optimal transient performance that includes improvement in rise time, overshoot and settling time for the envelope tracking supply in linear power amplifiers. For this purpose, we propose an on-demand current source module: the bang-bang transient performance enhancer (BBTPE). Its objective is to follow fast variations in input signals with reduced overshoot and settling time without deteriorating the steady-state performance of the buck regulator. The proposed approach enables fast system response through the BBTPE and an accurate steady-state output response through a low switching ripple and power efficient dynamic buck regulator. Fast output response with the help of the added module induces a slower rise of inductor current in the buck converter that further helps the proposed system to reduce both overshoot and settling time. This article also introduces an efficient selective tracking of envelope signal for linear PAs. To demonstrate the feasibility of the proposed solution, extensive simulations and experimental results from a discrete system are reported. The proposed supply modulator shows 80% improvement in rise time along with 60% reduction in both overshoot and settling time compared to the conventional dynamic buck regulator-based solution. Experimental results using the LTE 16-QAM 5 MHz standard shows improvement of 7.68 dB and 65.1% in adjacent channel power ratio (ACPR) and error vector magnitude (EVM), respectively.Peer ReviewedPostprint (author's final draft

RF Power Amplifier and Its Envelope Tracking

This dissertation introduces an agile supply modulator with optimal transient performance for the envelope tracking supply in linear power amplifiers. For this purpose, an on-demand current source module, the bang-bang transient performance enhancer (BBTPE), is proposed. Its objective is to follow fast variations in input signals with reduced overshoot and settling time without deteriorating the steady-state performance of the buck regulator. The proposed approach enables fast system response through the BBTPE and an accurate steady-state output response through a low switching ripple and power efficient dynamic buck regulator. Fast output response with the help of the added module induces a slower rise of inductor current in the buck converter that further assists the proposed system to reduce both overshoot and settling time. To demonstrate the feasibility of the proposed solution, extensive simulations and experimental results from a discrete system are reported. The proposed supply modulator shows 80% improvement in rise time along with 60% reduction in both overshoot and settling time compared to the conventional dynamic buck regulator-based solution. Experimental results for a PA using the LTE 16-QAM 5 MHz standard shows improvement of 7.68 dB and 65.1% in ACPR and EVM, respectively. In a polar power amplifier, the input signal splits into phase and amplitude components using a non-linear conversion operation. This operation broadens the spectrum of the polar signal components. The information of amplitude and phase contains spectral images due to the sampling operation in non-linear conversion operation. These spectral images can be large and cause out-of-band emission in the output spectrum. In addition, during the recombination process of phase and amplitude, a delay mismatch between amplitude and phase signals, which can occur due to separate processing paths of amplitude and phase signals, causes out-of-band emissions, also known as spectral regrowth. This dissertation presents solutions to both of the issues of digital polar power amplifier: spectral images and delay mismatch. In order to reduce the problem of spectral images, interpolation of phase and amplitude is proposed in this work. This increases the effective sampling frequency of the amplitude and phase, which helps to improve the linearity by around 10 dB. In addition, a novel calibration scheme is proposed here for the delay mismatch between phase and amplitude path in a digital polar power amplifier. The scheme significantly reduces the spectral regrowth. The scheme uses the same path for phase and amplitude delay calculation after the recombination that allows having a robust calibration. Furthermore, it can be executed during the empty transmission slots. The proposed scheme is designed in a 40 nm CMOS technology and simulated with a 64-QAM IEEE 802.11n wireless standard. The scheme achieved 7.57 dB enhancement in ACLR and 84.35% improvement in EVM for a 3.5 ns mismatch in phase and amplitude path

Partial least squares identification of multi look-up table digital predistorters for concurrent dual-band envelope tracking power amplifiers

©208 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.This paper presents a technique to estimate the coefficients of a multiple-look-up table (LUT) digital predistortion (DPD) architecture based on the partial least-squares (PLS) regression method. The proposed 3-D distributed memory LUT architecture is suitable for efficient FPGA implementation and compensates for the distortion arising in concurrent dual-band envelope tracking power amplifiers. On the one hand, a new variant of the orthogonal matching pursuit algorithm is proposed to properly select only the best LUTs of the DPD function in the forward path, and thus reduce the number of required coefficients. On the other hand, the PLS regression method is proposed to address both the regularization problem of the coefficient estimation and, at the same time, reducing the number of coefficients to be estimated in the DPD feedback identification path. Moreover, by exploiting the orthogonality of the PLS transformed matrix, the computational complexity of the parameters' identification can be significantly simplified. Experimental results will prove how it is possible to reduce the DPD complexity (i.e., the number of coefficients) in both the forward and feedback paths while meeting the targeted linearity levels.Peer ReviewedPostprint (author's final draft