RF to Millimeter-wave Linear Power Amplifiers in Nanoscale CMOS SOI Technology

The low manufacturing cost, integration capability with baseband and digital circuits, and high operating frequency of nanoscale CMOS technologies have propelled their applications into RF and microwave systems. Implementing fully-integrated RF to millimeter-wave (mm-wave) CMOS power amplifiers (PAs), nevertheless, remains challenging due to the low breakdown voltages of CMOS transistors and the loss from on-chip matching networks. These limitations have reduced the design space of CMOS power amplifiers to narrow-band, low linearity metrics often with insufficient gain, output power, and efficiency. A new topology for implementing power amplifiers based on stacking of CMOS SOI transistors is proposed. The input RF power is coupled to the transistors using on-chip transformers, while the gate terminal of teach transistor is dynamically biased from the output node. The output voltages of the stacked transistors are added constructively to increase the total output voltage swing and output power. Moreover, the stack configuration increases the optimum load impedance of the PA to values close to 50 ohm, leading to power, efficiency and bandwidth enhancements. Practical design issues such as limitation in the number of stacked transistors, gate oxide breakdown, stability, effect of parasitic capacitances on the performance of the PA and large chip areas have also been addressed. Fully-integrated RF to mm-wave frequency CMOS SOI PAs are successfully implemented and measured using the proposed topology

A digital polar transmitter for multi-band OFDM Ultra-WideBand

Linear power amplifiers used to implement the Ultra-Wideband standard must be backed off from optimum power efficiency to meet the standard specifications and the power efficiency suffers. The problem of low efficiency can be mitigated by polar modulation. Digital polar architectures have been employed on numerous wireless standards like GSM, EDGE, and WLAN, where the fractional bandwidths achieved are only about 1%, and the power levels achieved are often in the vicinity of 20 dBm. Can the architecture be employed on wireless standards with low-power and high fractional bandwidth requirements and yet achieve good power efficiency? To answer these question, this thesis studies the application of a digital polar transmitter architecture with parallel amplifier stages for UWB. The concept of the digital transmitter is motivated and inspired by three factors. First, unrelenting advances in the CMOS technology in deep-submicron process and the prevalence of low-cost Digital Signal processing have resulted in the realization of higher level of integration using digitally intensive approaches. Furthermore, the architecture is an evolution of polar modulation, which is known for high power efficiency in other wireless applications. Finally, the architecture is operated as a digital-to-analog converter which circumvents the use of converters in conventional transmitters. Modeling and simulation of the system architecture is performed on the Agilent Advanced Design System Ptolemy simulation platform. First, by studying the envelope signal, we found that envelope clipping results in a reduction in the peak-to-average power ratio which in turn improves the error vector magnitude performance (figure of merit for the study). In addition, we have demonstrated that a resolution of three bits suffices for the digital polar transmitter when envelope clipping is performed. Next, this thesis covers a theoretical derivation for the estimate of the error vector magnitude based on the resolution, quantization and phase noise errors. An analysis on the process variations - which result in gain and delay mismatches - for a digital transmitter architecture with four bits ensues. The above studies allow RF designers to estimate the number of bits required and the amount of distortion that can be tolerated in the system. Next, a study on the circuit implementation was conducted. A DPA that comprises 7 parallel RF amplifiers driven by a constant RF phase-modulated signal and 7 cascode transistors (individually connected in series with the bottom amplifiers) digitally controlled by a 3-bit digitized envelope signal to reconstruct the UWB signal at the output. Through the use of NFET models from the IBM 130-nm technology, our simulation reveals that our DPA is able to achieve an EVM of - 22 dB. The DPA simulations have been performed at 3.432 GHz centre frequency with a channel bandwidth of 528 MHz, which translates to a fractional bandwidth of 15.4%. Drain efficiencies of 13.2/19.5/21.0% have been obtained while delivering -1.9/2.5/5.5 dBm of output power and consuming 5/9/17 mW of power. In addition, we performed a yield analysis on the digital polar amplifier, based on unit-weighted and binary-weighted architecture, when gain variations are introduced in all the individual stages. The dynamic element matching method is also introduced for the unit-weighted digital polar transmitter. Monte Carlo simulations reveal that when the gain of the amplifiers are allowed to vary at a mean of 1 with a standard deviation of 0.2, the binary-weighted architecture obtained a yield of 79%, while the yields of the unit-weighted architectures are in the neighbourhood of 95%. Moreover, the dynamic element matching technique demonstrates an improvement in the yield by approximately 3%. Finally, a hardware implementation for this architecture based on software-defined arbitrary waveform generators is studied. In this section, we demonstrate that the error vector magnitude results obtained with a four-stage binary-weighted digital polar transmitter under ideal combining conditions fulfill the European Computer Manufacturers Association requirements. The proposed experimental setup, believed to be the first ever attempted, confirm the feasibility of a digital polar transmitter architecture for Ultra-Wideband. In addition, we propose a number of power combining techniques suitable for the hardware implementation. Spatial power combining, in particular, shows a high potential for the digital polar transmitter architecture. The above studies demonstrate the feasibility of the digital polar architecture with good power efficiency for a wideband wireless standard with low-power and high fractional bandwidth requirements

High Performance RF and Basdband Analog-to-Digital Interface for Multi-standard/Wideband Applications

The prevalence of wireless standards and the introduction of dynamic standards/applications, such as software-defined radio, necessitate the next generation wireless devices that integrate multiple standards in a single chip-set to support a variety of services. To reduce the cost and area of such multi-standard handheld devices, reconfigurability is desirable, and the hardware should be shared/reused as much as possible. This research proposes several novel circuit topologies that can meet various specifications with minimum cost, which are suited for multi-standard applications. This doctoral study has two separate contributions: 1. The low noise amplifier (LNA) for the RF front-end; and 2. The analog-to-digital converter (ADC). The first part of this dissertation focuses on LNA noise reduction and linearization techniques where two novel LNAs are designed, taped out, and measured. The first LNA, implemented in TSMC (Taiwan Semiconductor Manufacturing Company) 0.35Cm CMOS (Complementary metal-oxide-semiconductor) process, strategically combined an inductor connected at the gate of the cascode transistor and the capacitive cross-coupling to reduce the noise and nonlinearity contributions of the cascode transistors. The proposed technique reduces LNA NF by 0.35 dB at 2.2 GHz and increases its IIP3 and voltage gain by 2.35 dBm and 2dB respectively, without a compromise on power consumption. The second LNA, implemented in UMC (United Microelectronics Corporation) 0.13Cm CMOS process, features a practical linearization technique for high-frequency wideband applications using an active nonlinear resistor, which obtains a robust linearity improvement over process and temperature variations. The proposed linearization method is experimentally demonstrated to improve the IIP3 by 3.5 to 9 dB over a 2.5–10 GHz frequency range. A comparison of measurement results with the prior published state-of-art Ultra-Wideband (UWB) LNAs shows that the proposed linearized UWB LNA achieves excellent linearity with much less power than previously published works. The second part of this dissertation developed a reconfigurable ADC for multistandard receiver and video processors. Typical ADCs are power optimized for only one operating speed, while a reconfigurable ADC can scale its power at different speeds, enabling minimal power consumption over a broad range of sampling rates. A novel ADC architecture is proposed for programming the sampling rate with constant biasing current and single clock. The ADC was designed and fabricated using UMC 90nm CMOS process and featured good power scalability and simplified system design. The programmable speed range covers all the video formats and most of the wireless communication standards, while achieving comparable Figure-of-Merit with customized ADCs at each performance node. Since bias current is kept constant, the reconfigurable ADC is more robust and reliable than the previous published works

Vidutinių dažnių 5G belaidžių tinklų galios stiprintuvų tyrimas

This dissertation addresses the problems of ensuring efficient radio fre-quency transmission for 5G wireless networks. Taking into account, that the next generation 5G wireless network structure will be heterogeneous, the device density and their mobility will increase and massive MIMO connectivity capability will be widespread, the main investigated problem is formulated – increasing the efficiency of portable mid-band 5G wireless network CMOS power amplifier with impedance matching networks. The dissertation consists of four parts including the introduction, 3 chapters, conclusions, references and 3 annexes. The investigated problem, importance and purpose of the thesis, the ob-ject of the research methodology, as well as the scientific novelty are de-fined in the introduction. Practical significance of the obtained results, defended state-ments and the structure of the dissertation are also included. The first chapter presents an extensive literature analysis. Latest ad-vances in the structure of the modern wireless network and the importance of the power amplifier in the radio frequency transmission chain are de-scribed in detail. The latter is followed by different power amplifier archi-tectures, parameters and their improvement techniques. Reported imped-ance matching network design methods are also discussed. Chapter 1 is concluded distinguishing the possible research vectors and defining the problems raised in this dissertation. The second chapter is focused around improving the accuracy of de-signing lumped impedance matching network. The proposed methodology of estimating lumped inductor and capacitor parasitic parameters is dis-cussed in detail provi-ding complete mathematical expressions, including a summary and conclusions. The third chapter presents simulation results for the designed radio fre-quency power amplifiers. Two variations of Doherty power amplifier archi-tectures are presented in the second part, covering the full step-by-step de-sign and simulation process. The latter chapter is concluded by comparing simulation and measurement results for all designed radio frequency power amplifiers. General conclusions are followed by an extensive list of references and a list of 5 publications by the author on the topic of the dissertation. 5 papers, focusing on the subject of the discussed dissertation, have been published: three papers are included in the Clarivate Analytics Web of Sci-ence database with a citation index, one paper is included in Clarivate Ana-lytics Web of Science database Conference Proceedings, and one paper has been published in unreferred international conference preceedings. The au-thor has also made 9 presentations at 9 scientific conferences at a national and international level.Dissertatio

Low-noise amplifiers for integrated multi-mode direct-conversion receivers

The evolution of wireless telecommunication systems during the last decade has been rapid. During this time the design driver has shifted towards fast data applications instead of speech. In addition, the different systems may have a limited coverage, for example, limited to urban areas only. Thus, it has become important for a mobile terminal to be able to use different wireless systems, depending on the application chosen and the location of the terminal. The choice of receiver architecture affects the performance, size, and cost of the receiver. The superheterodyne receiver has hitherto been the dominant radio architecture, because of its good sensitivity and selectivity. However, superheterodyne receivers require expensive filters, which, with the existing technologies, cannot be integrated on the same chip as the receiver. Therefore, architectures using a minimum number of external components, such as direct conversion, have become popular. In addition, compared to the superheterodyne architecture, the direct-conversion architecture has benefits when multi-mode receivers, which are described in this thesis, are being designed. In this thesis, the limitations placed on the analog receiver by different system specifications are introduced. The estimations for the LNA specifications are derived from these specifications. In addition, the limitations imposed by different types of receiver architectures are described. The inductively-degenerated LNA is the basis for all the experimental circuits. The different components for this configuration are analyzed and compared to other commonly-used configurations in order to justify the use of an inductively-degenerated LNA. Furthermore, the design issues concerning the LNA-mixer interface in direct-conversion receivers are analyzed. Without knowing these limitations, it becomes difficult to understand the choices made in the experimental circuits. One of the key parts of this thesis describes the design and implementation of a single-chip multi-mode LNA, which is one of the key blocks in multi-mode receivers. The multi-mode structures in this thesis were developed for a direct-conversion receiver where only one system is activated at a time. The LNA interfaces to a pre-select filter and mixers and the different LNA components are analyzed in detail. Furthermore, the design issues related to possible interference from additional systems on single-chip receivers are analyzed and demonstrated. A typical receiver includes variable gain, which can be implemented both in the analog baseband and/or in the RF. If the variable gain is implemented in the RF parts, it is typically placed in the LNA or in a separate gain control stage. Several methods that can be used to implement a variable gain in the LNA are introduced and compared to each other. Furthermore, several of these methods are included in the experimental circuits. The last part of this thesis concentrates on four experimental circuits, which are described in this thesis. The first two chips describe an RF front-end and a direct-conversion receiver for WCDMA applications. The whole receiver demonstrates that it is possible to implement A/D converters on the same chip as sensitive RF blocks without significantly degrading receiver performance. The other two chips describe an RF front-end for WCDMA and GSM900 applications and a direct-conversion receiver for GSM900, DCS1800, PCS1900 and WCDMA systems. These ICs demonstrate the usability of the circuit structure developed and presented in this thesis. The chip area in the last multi-mode receiver is not significantly increased compared to corresponding single-system receivers.reviewe

Configurable circuits and their impact on multi-standard RF front-end architectures

This thesis studies configurable circuits and their impact on multi-standard RF front-end architectures. In particular, low-voltage low-power linear LNA and mixer topologies suitable for implementation in multi-standard front-ends are subject of the investigation. With respect to frequency and bandwidth, multi-standard front-ends can be implemented using either tunable or wideband LNA and mixer topologies. Based on the type of the LNA and mixer(s), multi-standard receiver RF front-ends can be divided into three groups. They can be (tunable) narrow-band, wide-band or combined. The advantages and disadvantages of the different multi-standard receiver RF front-ends have been discussed in detail. The partitioning between off-chip selectivity, on-chip selectivity provided by the LNA and mixer, linearity, power consumption and occupied chip area in each multi-standard RF front-end group are thoroughly investigated. A Figure of Merit (FOM) for the multi-standard receiver RF front-end has been introduced. Based on this FOM the most suitable multi-standard RF front-end group in terms of cost-effectiveness can be selected. In order to determine which multi-standard RF front-end group is the most cost-effective for a practical application, a GSM850/E-GSM/DCS/PCS/Bluetooth/WLANa/b/g multi-standard receiver RF front-end is chosen as a demonstrator. These standards are the most frequently used standards in wireless communication, and this combination of standards allows to users almost "anytime-anywhere" voice and data transfer. In order to verify these results, three demonstrators have been defined, designed and implemented, two wideband RF front-end circuits in 90nm CMOS and 65nm CMOS, and one combined multi-standard RF front-end circuit in 65nm CMOS. The proposed multi-standard demonstrators have been compared with the state-of the art narrow-band, wide-band and combined multi-standard RF front-ends. On the proposed multi-standard RF front-ends and the state-of the art multi-standard RF front-ends the proposed FOM have been applied. The comparison shows that the combined multi-standard RF front-end group is the most cost effective multi-standard group for this application

Design of CMOS transimpedance amplifiers for remote antenna units in fiber-wireless systems.

La memoria de la tesis doctoral: Diseño de Amplificadores de Transimpedancia para Unidades de Antena Remota en Sistemas Fibra-Inalámbrico, se presenta en la modalidad de compendio de Publicaciones. A continuación, se expone un resumen del contexto, motivation y objetivos de la tesis.A lo largo de las últimas décadas, los avances tecnológicos y el esfuerzo por desarrollar nuevos sistemas de comunicaciones han crecido al ritmo que la demanda de información aumentaba a nivel mundial. Desde la aparición de Internet, el tráfico global de datos ha incrementado de forma exponencial y se han creado infinidad de aplicaciones y contenidos desde entonces.Con la llegada de la fibra óptica se produjo un avance muy significativo en el campo de las comunicaciones, ya que la fibra de vidrio y sus características fueron la clave para crear redes de largo alcance y alta velocidad. Por otro lado, los avances en las tecnologías de fabricación de circuitos integrados y de dispositivos fotónicos de alta velocidad han encabezado el desarrollo de los sistemas de comunicaciones ópticos, logrando incrementar la tasa de transmisión de datos hasta prácticamente alcanzar el ancho de banda de la fibra óptica.Para conseguir una mayor eficiencia en las comunicaciones y aumentar la tasa de transferencia, se necesitan métodos de modulación complejos que aprovechen mejor el ancho de banda disponible. No obstante, esta mayor complejidad de la modulación de los datos requiere sistemas con mejores prestaciones en cuanto a rango dinámico y linealidad. Estos esquemas de modulación se emplean desde hace tiempo en los sistemas de comunicaciones inalámbricos, donde el ancho de banda del canal, el aire, es extremadamente limitado y codiciado.Actualmente, los sistemas inalámbricos se enfrentan a una saturación del espectro que supone un límite a la tasa de transmisión de datos. Pese a los esfuerzos por extender el rango frecuencial a bandas superiores para aumentar el ancho de banda disponible, se espera un enorme aumento tanto en el número de dispositivos, como en la cantidad de datos demandados por usuario.Ante esta situación se han planteado distintas soluciones para superar estas limitaciones y mejorar las prestaciones de los sistemas actuales. Entre estas alternativas están los sistemas mixtos fibra-inalámbrico utilizando sistemas de antenas distribuidas (DAS). Estos sistemas prometen ser una solución económica y muy efectiva para mejorar la accesibilidad de los dispositivos inalámbricos, aumentando la cobertura y la tasa de transferencia de las redes a la vez que disminuyen las interferencias. El despliegue de los DAS tendrá un gran efecto en escenarios tales como edificios densamente poblados, hospitales, aeropuertos o edificios de oficinas, así como en áreas residenciales, donde un gran número de dispositivos requieren una cada vez mayor interconectividad.Dependiendo del modo de transmisión de los datos a través de la fibra, los sistemas mixtos fibra-inalámbrico se pueden categorizar de tres formas distintas: Banda base sobre fibra (BBoF), radiofrecuencia sobre fibra (RFoF) y frecuencia intermedia sobre fibra (IFoF). Actualmente, el esquema BBoF es el más utilizado para transmisiones de larga y media distancia. No obstante, utilizar este esquema en un DAS requiere unidades de antena remota (RAU) complejas y costosas, por lo que no está claro que esta configuración pueda ser viable en aplicaciones de bajo coste que requieran de un gran número de RAUs. Los sistemas RFoF e IFoF presentan esquemas más simples, sin necesidad de integrar un modulador/demodulador, puesto que la señal se procesa en una estación base y no en las propias RAUs.El desarrollo de esta tesis se enmarca en el estudio de los distintos esquemas de DAS. A lo largo de esta tesis se presentan varias propuestas de amplificadores de transimpedancia (TIA) adecuadas para su implementación en cada uno de los tres tipos de RAU existentes. La versatilidad y el amplio campo de aplicación de este circuito integrado, tanto en comunicaciones como en otros ámbitos, han motivado el estudio de la implementación de este bloque específico en las diferentes arquitecturas de RAU y en otros sistemas, tales como un receptor de televisión por cable (CATV) o una interfaz de un microsensor inercial capacitivo.La memoria de tesis se ha dividido en tres capítulos. El Capítulo 1 se ha empleado para introducir el concepto de los DAS, proporcionando el contexto y la motivación del diseño de las RAU, partiendo desde los principios básicos de operación de los dispositivos fotónicos y electrónicos y presentando las distintas arquitecturas de RAU. El Capítulo 2 supone el núcleo principal de la tesis. En este capítulo se presenta el estudio y diseño de los diferentes TIAs, que han sido optimizados respectivamente para cada una de las configuraciones de RAU, así como para otras aplicaciones. En un tercer capítulo se recogen los resultados más relevantes y se exponen las conclusiones de este trabajo.Tras llevar a cabo la descripción y comparación de las topologías existentes de TIA, se ha llegado a las siguientes conclusiones, las cuales nos llevan a elegir la topología shunt-feedback como la más adecuada para el diseño: - El compromiso entre ancho de banda, transimpedancia, consumo de potencia y ruido es menos restrictivo en los TIAs de lazo cerrado. - Los TIAs de lazo cerrado tienen un mayor número de grados de libertad para acometer su diseño. - Esta topología presenta una mejor linealidad gracias al lazo de realimentación. Si la respuesta frecuencial del núcleo del amplificador se ajusta de manera adecuada, el TIA shunt-feedback puede presentar una respuesta frecuencial plana y estable.En esta tesis, se ha propuesto una nueva técnica de reducción de ruido, aplicable en receptores ópticos con fotodiodos con un área activa grande (~1mm2). Esta estrategia, que se ha llamado la técnica del fotodiodo troceado, consiste en la fabricación del fotodiodo, no como una estructura única, sino como un array de N sub-fotodiodos, que ocuparían la misma área activa que el original. Las principales conclusiones tras hacer un estudio teórico y realizar un estudio de su aplicación en una de las topologías de TIA propuestas son: - El ruido equivalente a la entrada es menor cuanto mayor es el número de sub-fotodiodos, dado que la contribución al ruido que depende con el cuadrado de la frecuencia (f^2) decrece con una dependencia proporcional a N. - Con una aplicación simple de la técnica, replicando el amplificador de tensión del TIA N veces y utilizando N resistencias de realimentación, cada una con un valor N veces el original, la sensibilidad del receptor aumenta aproximadamente en un factor √N y la estabilidad del sistema no se ve afectada. - Al dividir el fotodiodo en N sub-fotodiodos, la capacidad parásita de cada uno de ellos es N veces menor a la original. Con esta nueva capacidad parásita, el diseño del TIA se puede optimizar, consiguiendo una sensibilidad mucho mejor que con un único fotodiodo para el mismo valor de consumo de potencia.Las principales conclusiones respecto a los diseños de los distintos TIAs para comunicaciones son las siguientes: TIA para BBoF: - El TIA propuesto, alcanza, con un consumo de tan solo 2.9 mW, un ancho de banda de 1 GHz y una sensibilidad de -11 dBm, superando las características de trabajos anteriores en condiciones similares (capacidad del fotodiodo, tecnología y tasa de transmisión). - La técnica del fotodiodo troceado se ha aplicado a este circuito, consiguiendo una mejora de hasta 7.9 dBm en la sensibilidad para un diseño optimizado de 16 sub-fotodiodos, demostrando, en una simulación a nivel de transistor, que la técnica propuesta funciona correctamente. TIA para RFoF: - El diseño propuesto logra una figura de mérito superior a la de trabajos previos, gracias a la combinación de su bajo consumo de potencia y su mayor transimpedancia. - Además, mientras que en la mayoría de trabajos previos no se integra un control de ganancia en el TIA, esta propuesta presenta una transimpedancia controlable desde 45 hasta 65 dBΩ. A través de un sistema de control simultáneo de la transimpedancia y de la ganancia en lazo abierto del amplificador de voltaje, se consigue garantizar una respuesta frecuencial plana y estable en todos los estados de transimpedancia, que le otorga al diseño una superior versatilidad y flexibilidad. TIA para CATV: - Se ha adaptado una versión del TIA para RFoF para demostrar la capacidad de adaptación de esta estructura en una implementación en un receptor CATV con un rango de control de transimpedancia de 18 dB. - Con la implementación del control de ganancia en el TIA, no es necesario el uso de un atenuador variable en el receptor, simplificando así el número de etapas del mismo. - Gracias al control de transimpedancia, el TIA logra rangos de entrada similares a los publicados en trabajos anteriores basados en una tecnología mucho menos accesible como GaAs PHEMT. TIA para IFoF Se ha fabricado un chip en una tecnología CMOS de 65 nm que opera a 1.2 V de tensión de alimentación y se ha realizado su caracterización eléctrica y óptica. - El TIA presenta una programabilidad de su transimpedancia con un control lineal en dB entre 60 y 76 dBΩ mediante un código termómetro de 4 bits. - El ancho de banda se mantiene casi constante en todo el rango de transimpedancia, entre 500 y 600 MHz.Como conclusión general tras comparar el funcionamiento de los TIAs para las distintas configuraciones de RAU, vale la pena mencionar que el TIA para IFoF consigue una figura de mérito muy superior a la de otros trabajos previos diseñados para RFoF. Esto se debe principalmente a la mayor transimpedancia y al muy bajo consumo de potencia del TIA para IFoF propuesto. Además, se consigue una mejor linealidad, ya que, para una transmisión de 54 Mb/s con el estándar 802.11a, se consigue un EVM menor de 2 % en un rango de entrada de 10 dB, comparado con los entre 3 y 5 dB reportados en trabajos previos. El esquema IFoF presenta un gran potencial y ventajas frente al RFoF, lo que lo coloca como una buena alternativa para disminuir los costes y mejorar el rendimiento de los sistemas de antenas distribuidas.Por último, cabe destacar que el diseño de TIA propuesto y fabricado para IFoF contribuye en gran medida al desarrollo y validación de una RAU completa. Se ha demostrado la capacidad de la estructura propuesta para alcanzar un bajo ruido, alta linealidad, simplicidad en la programabilidad de la transimpedancia y adaptabilidad de la topología para diferentes requisitos, lo cual es de un gran interés en el diseño de receptores ópticos.Por otra parte, una versión del TIA para su uso en una interfaz de sensores MEMS capacitivos se ha propuesto y estudiado. Consiste en un convertidor capacidad-voltaje basado en una versión del TIA para RFoF, con el objetivo de conseguir un menor ruido y proveer de una adaptabilidad para diferentes sensores capacitivos. Los resultados más significativos y las conclusiones de este diseño se resumen a continuación: - El TIA presenta un control de transimpedancia con un rango de 34 dB manteniendo el ancho de banda constante en 1.2 MHz. También presenta un control independiente del ancho de banda, desde 75 kHz hasta 1.2 MHz, manteniendo la transimpedancia fija en un valor máximo. - Con un consumo de potencia de tan solo 54 μW, el TIA alcanza una sensibilidad máxima de 1 mV/fF, que corresponde a una sensibilidad de 4.2 mV/g y presenta un ruido de entrada de tan solo 100 µg/√("Hz" ) a 50 kHz en la configuración de máxima transimpedancia.La principal conclusión que destaca de este diseño es su versatilidad y flexibilidad. El diseño propuesto permite adaptar fácilmente la respuesta de la interfaz a una amplia gama de dispositivos sensores, ya que se puede ajustar el ancho de banda para ajustarse a distintas frecuencias de operación, así como la transimpedancia puede ser modificada para conseguir distintas sensibilidades. Este doble control independiente de ancho de banda y transimpedancia le proporcionan una adaptabilidad completa al TIA.<br /

Advances in Integrated Circuit Design and Implementation for New Generation of Wireless Transceivers

User’s everyday outgrowing demand for high-data and high performance mobile devices pushes industry and researchers into more sophisticated systems to fulfill those expectations. Besides new modulation techniques and new system designs, significant improvement is required in the transceiver building blocks to handle higher data rates with reasonable power efficiency. In this research the challenges and solution to improve the performance of wireless communication transceivers is addressed. The building block that determines the efficiency and battery life of the entire mobile handset is the power amplifier. Modulations with large peak to average power ratio severely degrade efficiency in the conventional fixed-biased power amplifiers (PAs). To address this challenge, a novel PA is proposed with an adaptive load for the PA to improve efficiency. A nonlinearity cancellation technique is also proposed to improve linearity of the PA to satisfy the EVM and ACLR specifications. Ultra wide-band (UWB) systems are attractive due to their ability for high data rate, and low power consumption. In spite of the limitation assigned by the FCC, the coexistence of UWB and NB systems are still an unsolved challenge. One of the systems that is majorly affected by the UWB signal, is the 802.11a system (5 GHz Wi-Fi). A new analog solution is proposed to minimize the interference level caused by the impulse Radio UWB transmitter to nearby narrowband receivers. An efficient 400 Mpulse/s IR-UWB transmitter is implemented that generates an analog UWB pulse with in-band notch that covers the majority of the UWB spectrum. The challenge in receiver (RX) design is the over increasing out of blockers in applications such as cognitive and software defined radios, which are required to tolerate stronger out-of-band (OB) blockers. A novel RX is proposed with a shunt N-path high-Q filter at the LNA input to attenuate OB-blockers. To further improve the linearity, a novel baseband blocker filtering techniques is proposed. A new TIA has been designed to maintain the good linearity performance for blockers at large frequency offsets. As a result, a +22 dBm IIP3 with 3.5 dB NF is achieved. Another challenge in the RX design is the tough NF and linearity requirements for high performance systems such as carrier aggregation. To improve the NF, an extra gain stage is added after the LNA. An N-path high-Q band-pass filter is employed at the LNA output together with baseband blocker filtering technique to attenuate out-of-band blockers and improve the linearity. A noise-cancellation technique based on the frequency translation has been employed to improve the NF. As a result, a 1.8dB NF with +5 dBm IIP3 is achieved. In addition, a new approach has been proposed to reject out of band blockers in carrier aggregation scenarios. The proposed solution also provides carrier to carrier isolation compared to typical solution for carrier aggregation

Parallel integrated receivers for multiple antenna wireless LAN systems

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.Includes bibliographical references (p. 147-154).This thesis focuses on the design of power- and area-efficient parallel integrated receivers for multiple antenna wireless LAN systems. These receivers are part of an indoor parallel radio system that achieves 1 gigabit per second data rates and enables high bandwidth wireless communication between portable user devices and a high speed wired internet connection. Since a critical aspect for efficiency is that an optimal number of transceivers be used to meet system requirements, this thesis first considers power dissipation and area. consumption for parallel integrated transceivers. It develops parallel transceiver power dissipation and area consumption models that are functions of distance, data rate, and noise figure and incorporate the behavior of a multiple-input, multiple-output channel and power dissipation and area consumption values for typical RF circuits. These models properly balance benefits of multiple antennas with drawbacks due to parallel radio overhead. Their application shows that the combined transceiver power dissipation can actually decrease with more antennas and also provides a circuits-based number of antennas upper bound that has not been established previously.(cont.) The thesis then proposes a solution that applies multiple antenna signal-to-noise ratio (SNR) gain at the receiver to reduce its power dissipation and area consumption. SNR gain trades noise figure for power- and area-efficient circuits. The implementation of a, single chip 5.22-GHz area-efficient parallel receiver RFIC that shows practical application of these models, SNR gain, and area-efficient circuits is demonstrated. The context of this design comes from the Wireless Gigabit Local Area Network (WiGLAN). It's system characteristics such as a wide 150 MHz bandwidth and parallel radios uniquely determine a WiGLAN parallel receiver design.by Lunal Khuon.Ph.D

Highly efficient linear CMOS power amplifiers for wireless communications

The rapidly expanding wireless market requires low cost, high integration and high performance of wireless communication systems. CMOS technology provides benefits of cost effectiveness and higher levels of integration. However, the design of highly efficient linear CMOS power amplifier that meets the requirement of advanced communication standards is a challenging task because of the inherent difficulties in CMOS technology. The objective of this research is to realize PAs for wireless communication systems that overcoming the drawbacks of CMOS process, and to develop design approaches that satisfying the demands of the industry. In this dissertation, a cascode bias technique is proposed for improving linearity and reliability of the multi-stage cascode CMOS PA. In addition, to achieve load variation immunity characteristic and to enhance matching and stability, a fully-integrated balanced PA is implemented in a 0.18-m CMOS process. A triple-mode balanced PA using switched quadrature coupler is also proposed, and this work saved a large amount of quiescent current and further improved the efficiency in the back-off power. For the low losses and a high quality factor of passive output combining, a transformer-based quadrature coupler was implemented using integrated passive device (IPD) process. Various practical approaches for linear CMOS PA are suggested with the verified results, and they demonstrate the potential PA design approach for WCDMA applications using a standard CMOS technology.PhDCommittee Chair: Kenney, J. Stevenson; Committee Member: Jongman Kim; Committee Member: Kohl, Paul A.; Committee Member: Kornegay, Kevin T.; Committee Member: Lee, Chang-H