Towards fully integrated CMOS RF receivers

The evolution of the mobile telephony is demanding new multi-function terminals (cellular and cordless phones, GPS, pagers) compatible with a variety of standard (GSM, DCS, DECT, CDMA). At the same time the reduction of cost, size and power dissipation is mandatory. All this requires an higher integration level for the RF part, that is presently using a big number of components. This explains the big research effort put in silicon RF circuits particularly in CMOS technology. In this paper the state of the art of CMOS RF circuits is outlined. In particular some results regarding critical building blocks obtained by the STMicroelectronics and Pavia University research team are given. Future evelopments and the progress needed to successfully implement them are also pointed out

Minimum power design of RF front ends

This thesis describes an investigation into the design of RF front ends with minimum power dissipation. The central question is: "What are the fundamental limits for the power dissipation of telecommunication front ends, and what design procedures can be followed that approach these limits and, at the same time, result in practical circuits?" After a discussion of the state of the art in this area, the elementary operations of a front end are identified. For each of these elementary operations, the fundamental limits for the power dissipation are discussed, divided into technology imposed limits and physics imposed limits. A traditional DECT front end design is used to demonstrate the large difference between the fundamental limits and the power dissipation of existing circuits. To improve this situation, first the optimum distribution of specifications across individual subcircuits needs to be determined, such that the requirements for a specific system can be fulfilled. This is achieved through the introduction of formal transforms of the specifications of subcircuits, which correspond with transforms of the subcircuit itself. Using these transforms, the optimum distribution of gain, noise, linearity and power dissipation can be determined. As it turns out, this optimum distribution can even be represented by a simple, analytical expression. This expression predicts that the power dissipation of the DECT front end can be reduced by a factor of 2.7 through an optimum distribution of the specifications. Using these optimum specifications of the subcircuits, the boundaries for further power dissipation reduction can be determined. This is investigated at the system, circuit and technology level. These insights are used in the design of a 2.5GHz wireless local area network, implemented in an optimized technology ("Silicon on Anything"). The power dissipation of the complete receiver is 3.5mW, more than an order of magnitude below other wireless LAN receivers in recent publications. Finally, the combination of this minimum power design method with a platform based development strategy is discussed

Integrated radio frequency synthetizers for wireless applications

This thesis consists of six publications and an overview of the research topic, which is also a summary of the work. The research described in this thesis concentrates on the design of phase-locked loop radio frequency synthesizers for wireless applications. In particular, the focus is on the implementation of the prescaler, the phase detector, and the chargepump. This work reviews the requirements set for the frequency synthesizer by the wireless standards, and how these requirements are derived from the system specifications. These requirements apply to both integer-N and fractional-N synthesizers. The work also introduces the special considerations related to the design of fractional-N phase-locked loops. Finally, implementation alternatives for the different building blocks of the synthesizer are reviewed. The presented work introduces new topologies for the phase detector and the chargepump, and improved topologies for high speed CMOS prescalers. The experimental results show that the presented topologies can be successfully used in both integer-N and fractional-N synthesizers with state-of-the-art performance. The last part of this work discusses the additional considerations that surface when the synthesizer is integrated into a larger system chip. It is shown experimentally that the synthesizer can be successfully integrated into a complex transceiver IC without sacrificing the performance of the synthesizer or the transceiver.reviewe

A Fully-Integrated Quad-Band GSM/GPRS CMOS Power Amplifier

Concentric distributed active transformers (DAT) are used to implement a fully-integrated quad-band power amplifier (PA) in a standard 130 nm CMOS process. The DAT enables the power amplifier to integrate the input and output matching networks on the same silicon die. The PA integrates on-chip closed-loop power control and operates under supply voltages from 2.9 V to 5.5 V in a standard micro-lead-frame package. It shows no oscillations, degradation, or failures for over 2000 hours of operation with a supply of 6 V at 135° under a VSWR of 15:1 at all phase angles and has also been tested for more than 2 million device-hours (with ongoing reliability monitoring) without a single failure under nominal operation conditions. It produces up to +35 dBm of RF power with power-added efficiency of 51%