DESIGN OF A GAAS DISTRIBUTED AMPLIFIER WITH LC TRAPS BASED BROADBAND LINEARIZATION

Increasing the linearity of power amplifiers has been an important area of research because its signal integrity influences the performance of the entire transreceiver system and there are strict regulatory requirements on them. Due to the nonlinear behaviour of power amplifiers, third order intermodulation products are generated close to the desired signals and cannot be removed by filters. Increasing linearity will help bring these distortion products closer to the noise floor. However, it is not an easy task to increase linearity without trading off output power. To maintain the same level of output power generated but with higher linearity, many techniques, each with its own pros and cons, have been implemented to linearize an amplifier. Techniques involving feedback are seriously limited in terms of modulation bandwidth whereas methods such as predistortion and feedforward are very difficult to implement. This project seeks to use a simple method of placing terminations directly to the distributed amplifier (DA), making it a device level linearization technique and can be used in addition to the other system level techniques mentioned earlier. To increase linearity over a broad bandwidth of 0.5 to 3.0 GHz, this work proposes using low impedance terminations (LC traps) at the envelope frequency to the input and output of several distributed amplifiers. This research is novel since this is the first time broadband improvement in linearity has been demonstrated using the LC trap method. Two design iterations were completed (first design iteration has four variants to test the output trap while the second design iteration has three variants to test the input trap). The low impedance terminations are implemented using inductor-capacitor networks that are external to the monolithic microwave integrated circuit (MMIC). Design and layout of the DAs were carried out using Agilent’s Advanced Design System (ADS). Results show that placing the traps at the output of the DA does not truly affect the linearity of the device at lower frequencies but provide an improvement of 1.6 dB and 3.4 dB to the third-order output intercept point (OIP3) at 2.5 GHz and 3.0 GHz, respectively. With traps at the input, measurement results at -5 dBm input power, viii 1.375 V base bias (61 mA total collector current) and 10 MHz two tone spacing show a broadband improvement throughout the band (0.5 GHz to 3.0 GHz) of 3.3 dB to 7.4 dB in OIP3. Furthermore, the OIP3 is increased to 19.2 dB above P1dB. Results show that the improvement in OIP3 comes without lowering gain, return loss or P1dB and without causing any stability problems

Vidutinių dažnių 5G belaidžių tinklų galios stiprintuvų tyrimas

This dissertation addresses the problems of ensuring efficient radio fre-quency transmission for 5G wireless networks. Taking into account, that the next generation 5G wireless network structure will be heterogeneous, the device density and their mobility will increase and massive MIMO connectivity capability will be widespread, the main investigated problem is formulated – increasing the efficiency of portable mid-band 5G wireless network CMOS power amplifier with impedance matching networks. The dissertation consists of four parts including the introduction, 3 chapters, conclusions, references and 3 annexes. The investigated problem, importance and purpose of the thesis, the ob-ject of the research methodology, as well as the scientific novelty are de-fined in the introduction. Practical significance of the obtained results, defended state-ments and the structure of the dissertation are also included. The first chapter presents an extensive literature analysis. Latest ad-vances in the structure of the modern wireless network and the importance of the power amplifier in the radio frequency transmission chain are de-scribed in detail. The latter is followed by different power amplifier archi-tectures, parameters and their improvement techniques. Reported imped-ance matching network design methods are also discussed. Chapter 1 is concluded distinguishing the possible research vectors and defining the problems raised in this dissertation. The second chapter is focused around improving the accuracy of de-signing lumped impedance matching network. The proposed methodology of estimating lumped inductor and capacitor parasitic parameters is dis-cussed in detail provi-ding complete mathematical expressions, including a summary and conclusions. The third chapter presents simulation results for the designed radio fre-quency power amplifiers. Two variations of Doherty power amplifier archi-tectures are presented in the second part, covering the full step-by-step de-sign and simulation process. The latter chapter is concluded by comparing simulation and measurement results for all designed radio frequency power amplifiers. General conclusions are followed by an extensive list of references and a list of 5 publications by the author on the topic of the dissertation. 5 papers, focusing on the subject of the discussed dissertation, have been published: three papers are included in the Clarivate Analytics Web of Sci-ence database with a citation index, one paper is included in Clarivate Ana-lytics Web of Science database Conference Proceedings, and one paper has been published in unreferred international conference preceedings. The au-thor has also made 9 presentations at 9 scientific conferences at a national and international level.Dissertatio

Novel design & implementation of a broadband and highly efficient doherty power amplifier

Master'sMASTER OF ENGINEERIN

Improving linearity utilising adaptive predistortion for power amplifiers at mm-wave frequencies

The large unlicensed 3 GHz overlapping bandwidth that is available worldwide at 60 GHz has resulted in renewed interest in 60 GHz technology. This frequency band has made it attractive for short-range gigabit wireless communication. The power amplifier (PA) directly influences the performance and quality of this entire communication chain, as it is one of the final subsystems in the transmitter. Spectral efficient modulation schemes used at 60 GHz pose challenging requirements for the linearity of the PA. To improve the linearity, several external linearisation techniques currently exist, such as feedback, feedforward, envelope elimination and restoration, linear amplification with non-linear components and predistortion. This thesis is aimed at investigating and characterising the distortion components found in PAs at mm-wave frequencies and evaluating whether an adaptive predistortion (APD) linearisation technique is suitable to reduce these distortion components. After a thorough literature study and mathematical analysis, it was found that the third-order intermodulation distortion (IMD3) components were the most severe distortion components. Predistortion was identified as the most effective linearisation technique in terms of minimising these IMD3 components and was therefore proposed in this research. It does not introduce additional complexity and can easily be integrated with the PA. Furthermore, the approach is stable and has lower power consumption when compared to the aforementioned linearisation techniques. The proposed predistortion technique was developed compositely through this research by making it a function of the PA’s output power that was measured using a power detector. A comparator was used with the detected output power and the reference voltages to control the dynamic bias circuit of the variable gain amplifier. This provided control and flexibility on when to apply the predistortion to the PA and therefore allowing the linearity of the PA to be optimised. Three-stage non-linear and linear PAs were also designed at 60 GHz and implemented to compare the performance of the APD technique and form part of the hypothesis verification process. The 130 nm silicon-germanium (SiGe) bipolar and complementary metal oxide semiconductor (BiCMOS) technology from IBM was used for the simulation of the entire APD and PA design and for the fabrication of the prototype integrated circuits (ICs). This technology has the advantage of integrating the high performance, low power intensive SiGe heterojunction bipolar transistors (HBTs) with the CMOS technology. The SiGe HBTs have a high cut-off frequency (fT > 200 GHz), which is ideal for mm-wave PA applications and the CMOS components were integrated in the control logic of the digital circuitry. The simulations and IC layout were accomplished with Cadence Virtuoso. The implemented IC occupies an area of 1.8 mm by 2.0 mm. The non-linear PA achieves a Psat of 11.97 dBm and an IP1dB of -10 dBm. With the APD technique applied, the linearity of the PA is significantly improved with an IP1dB of -6 dBm and an optimum IMD3 reduction of 10 dB. Based on the findings and results of the applied APD technique, APD reduced intermodulation distortion (especially the IMD3) and is thus suitable to improve the linearity of PAs at mm-wave frequencies. To the knowledge of this author, no APD technique has been applied for PAs at 60 GHz, therefore the contribution of this research will assist future PA designers to characterise and optimise the reduction of the IMD3 components. This will result in improved linear output power from the PA and the use of complex modulation schemes at 60 GHz.Thesis (PhD)--University of Pretoria, 2014.Electrical, Electronic and Computer EngineeringPh

Highly efficient linear CMOS power amplifiers for wireless communications

The rapidly expanding wireless market requires low cost, high integration and high performance of wireless communication systems. CMOS technology provides benefits of cost effectiveness and higher levels of integration. However, the design of highly efficient linear CMOS power amplifier that meets the requirement of advanced communication standards is a challenging task because of the inherent difficulties in CMOS technology. The objective of this research is to realize PAs for wireless communication systems that overcoming the drawbacks of CMOS process, and to develop design approaches that satisfying the demands of the industry. In this dissertation, a cascode bias technique is proposed for improving linearity and reliability of the multi-stage cascode CMOS PA. In addition, to achieve load variation immunity characteristic and to enhance matching and stability, a fully-integrated balanced PA is implemented in a 0.18-m CMOS process. A triple-mode balanced PA using switched quadrature coupler is also proposed, and this work saved a large amount of quiescent current and further improved the efficiency in the back-off power. For the low losses and a high quality factor of passive output combining, a transformer-based quadrature coupler was implemented using integrated passive device (IPD) process. Various practical approaches for linear CMOS PA are suggested with the verified results, and they demonstrate the potential PA design approach for WCDMA applications using a standard CMOS technology.PhDCommittee Chair: Kenney, J. Stevenson; Committee Member: Jongman Kim; Committee Member: Kohl, Paul A.; Committee Member: Kornegay, Kevin T.; Committee Member: Lee, Chang-H

이동통신 기기에 적합한 재구성이 가능한 다중대역 선형 CMOS 전력증폭기에 관한 연구

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2015. 2. 권영우.In this Dissertation, a study on multiband reconfigurable linear CMOS power amplifier (PA) is performed. Since a larger number of frequency bands is allocated for 3G/4G mobile communication standards nowadays, handset PAs are required to support the ever-increasing number of frequency bands. With the advent of high-speed wireless data transmission, handset PAs are also demanded to perform linear power amplification under the wide-band signal condition. Even though the CMOS technology has cost and size benefits, however, designing a watt-level linear CMOS PA is a challenging issue due to low breakdown voltage and nonlinear nature of the CMOS device. To resolve the issues above, this study presents two methods suitable for multiband (MB) linear CMOS PA: a reconfigurable MB matching structure and a linearization technique. The proposed MB structure shares a PA core to reduce the cost and size, and contains the power- and frequency-reconfigurable matching networks as well as the output path-selection function. Thus, it can perform the MB operation requiring multiple frequency bands and target output powers. The reconfiguration mechanism is quantitatively analyzed and experimentally demonstrated. The fabricated tri-band reconfigurable 3G UMTS PA using an InGaP/GaAs heterojunction bipolar transistor (HBT) process for practical handset application showed minimal efficiency degradation of less than 2% by multi-banding, compared with a single-band reference PA. For linearization of a CMOS PA, a phase-based linearization technique is presented. Since the PA nonlinearity is determined by the dynamic AM-AM and AM-PM, the two distortions should simultaneously be considered in linearization. Contrary to the previous works which have focused on the correction of AM-AM distortion by providing an envelope-dependent gate-bias, this work proposes an AM-PM linearizer using a varactor and an envelope-reshaping circuit. This linearizer helps the PA recover AM-AM distortion as well. To validate the usefulness of the proposed linearizer, 1.88 GHz and 0.9 GHz stacked-FET PAs using a 0.32-μm silicon-on-insulator (SOI) CMOS process were designed and fabricated. Measurement results showed that the fabricated 1.88 / 0.9 GHz linear CMOS PAs achieved linear efficiencies (meeting –39 dBc W-CDMA ACLR) of higher than 44 / 49%. Furthermore, a single-chain MB linear CMOS PA was implemented based on the proposed MB reconfiguration and linearization techniques. The fabricated MB PA, which has two outputs and covers five popular uplink UMTS/LTE bands (Band 1/2/4/5/8: 824 ~ 1980 MHz), showed minimal efficiency degradation (< 3.3%) compared to the single-band dedicated CMOS PA with W-CDMA efficiencies in excess of 40.7%. Finally, the signal-bandwidth limiting effect of the envelope-based linear CMOS PA is discussed and a solution is proposed. Due to the time delay during envelope-detection and shaping, a timing mismatch between the incoming RF signal and envelope-reshaped signal occurs, thus resulting in no linearization effect under wide-band signal (LTE 20 MHz or more) conditions. To resolve the problem, a group delay circuit with a compact size is employed and thus the linearization effect of the proposed phase-based linearizer is maintained up to 40 MHz LTE bandwidth.Abstract i Contents iii List of Tables vi List of Figures vii 1. Introduction 1 1.1 Motivation 1 1.2 Multiband PA Structure 4 1.3 Linearization of CMOS PA 6 1.4 Dissertation Organization 7 1.5 References 9 2. A Multiband Reconfigurable Power Amplifier for 3G UMTS Handset Applications 10 2.1 Introduction 10 2.2 Operation Principle of the Reconfigurable Output Matching Network 12 2.2.1 Power Reconfigurable Network (PRN) 14 2.2.2 Frequency Reconfigurable Network (FRN) 17 2.2.3 Path Selection Network (PSN) 20 2.2.4 Experimental Validation of the PRN and FRN 24 2.3 Fabrication and Measurement of a MB UMTS Reconfigurable PA 26 2.3.1 Design 26 2.3.2 Measurement 31 2.4 Summary 37 2.5 References 38 3. Linearization of CMOS Power Amplifier and Its Multiband Application 41 3.1 Introduction 41 3.2 Linearization of CMOS PAs: Prior Arts 43 3.3 Harmonic Termination 46 3.3.1 Operation Analysis 47 3.3.2 Experimental Validation 52 3.4 Control of Gate Bias Modulation Effect 54 3.4.1 Analysis 54 3.4.2 Experimental Validation 60 3.5 Proposed Linearization #1: Hybrid Bias 67 3.6 Proposed Linearization #2: Phase Injection 71 3.6.1 Motivation 71 3.6.2 Phase (Capacitance) Injection 72 3.7 Linear CMOS PA Design 75 3.7.1 Baseline PA Design 76 3.7.2 Linearizer Design 78 3.7.3 Fabrication 82 3.8 Measurement Results 83 3.8.1 CW Measurement 83 3.8.2 W-CDMA Measurement 84 3.8.3 LTE Measurement 87 3.9 A Single-Chain MB Reconfigurable Linear PA in SOI CMOS 90 3.9.1 MB Linear CMOS PA: Design 90 3.9.2 MB Linear CMOS PA: Measurement 94 3.10 Summary 99 3.11 References 100 4. Linearization of CMOS Power Amplifier Convering Wideband Signal 105 4.1 Introduction 105 4.2 Bandwidth Limitation of Envelope-Based Linearizers 106 4.2.1 Analysis 106 4.2.2 Delay Correction 110 4.2.3 Feedforward Envelope-Detection Structure with a Delay T/L 114 4.3 Group Delay Circuit 117 4.3.1 Positive GDC versus Negative GDC 117 4.3.2 Left-Handed T/L-Based GDC 119 4.4 Fabrication and Measurement 122 4.4.1 GDC Measurement 123 4.4.2 LTE Measurement 124 4.5 Summary 127 4.6 References 128 5. Conclusions 130 5.1 Research Summary 130 5.2 Future Works 132 Abstract in Korean 133 Publications 135Docto

Design and characterization of downconversion mixers and the on-chip calibration techniques for monolithic direct conversion radio receivers

This thesis consists of eight publications and an overview of the research topic, which is also a summary of the work. The research described in this thesis is focused on the design of downconversion mixers and direct conversion radio receivers for UTRA/FDD WCDMA and GSM standards. The main interest of the work is in the 1-3 GHz frequency range and in the Silicon and Silicon-Germanium BiCMOS technologies. The RF front-end, and especially the mixer, limits the performance of direct conversion architecture. The most stringent problems are involved in the second-order distortion in mixers to which special attention has been given. The work introduces calibration techniques to overcome these problems. Some design considerations for front-end radio receivers are also given through a mixer-centric approach. The work summarizes the design of several downconversion mixers. Three of the implemented mixers are integrated as the downconversion stages of larger direct conversion receiver chips. One is realized together with the LNA as an RF front-end. Also, some stand-alone structures have been characterized. Two of the mixers that are integrated together with whole analog receivers include calibration structures to improve the second-order intermodulation rejection. A theoretical mismatch analysis of the second-order distortion in the mixers is also presented in this thesis. It gives a comprehensive illustration of the second-order distortion in mixers. It also gives the relationships between the dc-offsets and high IIP2. In addition, circuit and layout techniques to improve the LO-to-RF isolation are discussed. The presented work provides insight into how the mixer immunity against the second-order distortion can be improved. The implemented calibration structures show promising performance. On the basis of these results, several methods of detecting the distortion on-chip and the possibilities of integrating the automatic on-chip calibration procedures to produce a repeatable and well-predictable receiver IIP2 are presented.reviewe

Application of Nonlinear Transistor Characteristics

This research presents three works all related by the subject of third-order distortion reduction in nonlinear circuits. Each one is a novel extension to previous work in that branch of electronics literature. All three follow the procedure of presenting a novel algebraic proof and following up with simulations and/or measurements to confirm the theoretical result. The works are generally themed around nonlinear low-frequency bipolar transistor circuits. Firstly, an investigation is conducted into a well documented effect in bipolar-junction transistors (BJTs) called inherent third-order distortion nulling. This effect is shown to be a fundamental result of the transistor’s transfer junction acting upon an input signal. The proof of a single BJT emitter-follower amplifier’s inherent null is examined which is well documented in the literature. This forms the basis for a novel extension in Darlington transistors where theory suggests the third-order null occurs at double the collector current of a single BJT. Discrete measurements of a CA3083 transistor array are undertaken and compared with theory and simulation data. These measurements confirm theory with reasonable accuracy. A temperature and process variation independent bias circuit is developed to solve one issue with using third-order distortion nulling. This work is interesting in that it branches into series resistance compensation for translinear circuits and stands as a useful circuit in its own right. Using stacks of matched forward-biased semiconductor junctions which conform to translinear conditions, a bias current can be generated which theoretically removes temperature and series resistance dependence on the particular BJT used. This proves useful for the previous work in distortion nulling, but also allows direct and accurate measurement of series resistance. Again, simulation and measurement data is obtained from discrete measurements of the proposed circuit, and the results conform with theory to a reasonable degree. Lastly, this work presents the analysis of a cascoded-compensation (Cascomp) amplifier. It presents the first fully nonlinear derivation of the Cascomp’s transfer function and its associated harmonic and intermodulation distortion components. The derivation reveals an interesting characteristic in which the third-order intermodulation distortion has multiple local minima. This characteristic has not yet been presented in the literature, and allows better optimisation of Cascomp amplifiers in any application. Again, this characteristic and its potential benefits are confirmed with simulation and discrete measurements. Observations of the presented works are discussed and built upon in the last chapter. This leads to suggestions on future research topics branching on from these works