Techniques for Frequency Synthesizer-Based Transmitters.

Internet of Things (IoT) devices are poised to be the largest market for the semiconductor industry. At the heart of a wireless IoT module is the radio and integral to any radio is the transmitter. Transmitters with low power consumption and small area are crucial to the ubiquity of IoT devices. The fairly simple modulation schemes used in IoT systems makes frequency synthesizer-based (also known as PLL-based) transmitters an ideal candidate for these devices. Because of the reduced number of analog blocks and the simple architecture, PLL-based transmitters lend themselves nicely to the highly integrated, low voltage nanometer digital CMOS processes of today. This thesis outlines techniques that not only reduce the power consumption and area, but also significantly improve the performance of PLL-based transmitters.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/113385/1/mammad_1.pd

DDR5 클락 버퍼를 위한 LC PLL의 설계

학위논문(석사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022. 8. 정덕균.This thesis describes a wide-range, fast-locking LC PLL for DDR5 clock buffer application. To operate LC PLL at wide range of input frequency, proposed PLL uses LC VCO with 28GHz center frequency and calculates appropriate division ratio of programmable divider for certain input frequen-cy at transient state. Calculating division ratio is achieved by using integer counter and fractional counter, detecting frequency of input clock at transient state. After calculating division ratio, proposed PLL operates as 3rd order charge pump PLL with optimum current value to lock fast. Proposed PLL is described with Systemverilog and simulation results shows that proposed LC PLL operates at 1 ~ 4.2GHz input frequency, while successfully acquires to lock at under 1μs. Also, LC-VCO is designed in a 40nm CMOS and simulation results shows that tuning range of VCO is ±9.25% with respect to center frequency of 28.2GHz, and VCO dissipates 26.4mW and phase noise is –104.86dBc/Hz at 1MHz offset, operating at center fre-quency with 1.1V supply voltage.본 논문은 DDR5 Clock Buffer를 위한, 넓은 범위에서 빠르게 락을 하는 LC PLL에 대해서 설명한다. 넓은 범위의 입력 주파수에서 LC PLL을 동작하기 위해, 제안한 PLL은 28GHz가 중심 주파수인 LC VCO을 사용하여, 과도 상태에서 특정 입력 주파수에 알맞는 프로그램 가능한divider의 제수를 계산한다. 제수의 계산은 과도 상태에서 입력 클락의 주파수를 감지하는 정수 카운터와 소수 카운터를 통해 이루어진다. 제수의 계산 이후, 제안한 PLL은 빠르게 락을 하기 위한 최적의 전류 값으로 3차의 Charge pump PLL로 동작한다. 제안한 PLL은 systemverilog로 기술되었고 시뮬레이션 결과 제안한 LC PLL은 1 ~ 4.2GHz의 입력주파수에서 동작하며, 1us 이내에서 성공적으로 락을 한다. 또한, LC-VCO가 40nm CMOS 공정에서 설계되었고, 시뮬레이션 결과 VCO의 튜닝 범위가 중심 주파수 28.2GHz을 기준으로 ±9.25%이고, 중심 주파수와 1.1V 공급 전압에서 26.4mW의 전력을 소모하고, phase noise가 1MHz 오프셋에서 -104.86dBc/Hz임을 확인할 수 있었다.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 3 CHAPTER 2 BACKGROUND ON LC PLL 4 2.1 BASIS OF PLL 4 2.2 FREQUENCY RANGE AND LOCK TIME OF PLL 11 2.2.1 FREQUENCY RANGE 11 2.2.2 LOCK TIME 13 2.3 BASIS OF LC VCO 15 CHAPTER 3 DESIGN OF LC PLL FOR DDR5 CLOCK BUFFER 18 3.1 DESIGN CONSIDERATION 18 3.2 OVERALL ARCHITECTURE 20 3.3 OPERATION PRINCIPLE 24 3.4 IMPLEMENTATION OF LC VCO 33 3.5 ALTERNATIVE DESIGN CHOICE OF LC PLL FOR DDR5 CLOCK BUFFER 35 CHAPTER 4 SIMULATION RESULT 37 4.1 PLL 37 4.2 LC VCO 42 CHAPTER 5 CONCLUSION 46 BIBLIOGRAPHY 47 초 록 49석

Architectures and Circuits Leveraging Injection-Locked Oscillators for Ultra-Low Voltage Clock Synthesis and Reference-less Receivers for Dense Chip-to-Chip Communications

High performance computing is critical for the needs of scientific discovery and economic competitiveness. An extreme-scale computing system at 1000x the performance of today’s petaflop machines will exhibit massive parallelism on multiple vertical fronts, from thousands of computational units on a single processor to thousands of processors in a single data center. To facilitate such a massively-parallel extreme-scale computing, a key challenge is power. The challenge is not power associated with base computation but rather the problem of transporting data from one chip to another at high enough rates. This thesis presents architectures and techniques to achieve low power and area footprint while achieving high data rates in a dense very-short reach (VSR) chip-to-chip (C2C) communication network. High-speed serial communication operating at ultra-low supplies improves the energy-efficiency and lowers the power envelop of a system doing an exaflop of loops. One focus area of this thesis is clock synthesis for such energy-efficient interconnect applications operating at high speeds and ultra-low supplies. A sub-integer clockfrequency synthesizer is presented that incorporates a multi-phase injection-locked ring-oscillator-based prescaler for operation at an ultra-low supply voltage of 0.5V, phase-switching based programmable division for sub-integer clock-frequency synthesis, and automatic calibration to ensure injection lock. A record speed of 9GHz has been demonstrated at 0.5V in 45nm SOI CMOS. It consumes 3.5mW of power at 9.12GHz and 0.052 of area, while showing an output phase noise of -100dBc/Hz at 1MHz offset and RMS jitter of 325fs; it achieves a net of -186.5 in a 45-nm SOI CMOS process. This thesis also describes a receiver with a reference-less clocking architecture for high-density VSR-C2C links. This architecture simplifies clock-tree planning in dense extreme-scaling computing environments and has high-bandwidth CDR to enable SSC for suppressing EMI and to mitigate TX jitter requirements. It features clock-less DFE and a high-bandwidth CDR based on master-slave ILOs for phase generation/rotation. The RX is implemented in 14nm CMOS and characterized at 19Gb/s. It is 1.5x faster that previous reference-less embedded-oscillator based designs with greater than 100MHz jitter tolerance bandwidth and recovers error-free data over VSR-C2C channels. It achieves a power-efficiency of 2.9pJ/b while recovering error-free data (BER 200MHz and the INL of the ILO-based phase-rotator (32- Steps/UI) is <1-LSB. Lastly, this thesis develops a time-domain delay-based modeling of injection locking to describe injection-locking phenomena in nonharmonic oscillators. The model is used to predict the locking bandwidth, and the locking dynamics of the locked oscillator. The model predictions are verified against simulations and measurements of a four-stage differential ring oscillator. The model is further used to predict the injection-locking behavior of a single-ended CMOS inverter based ring oscillator, the lock range of a multi-phase injection-locked ring-oscillator-based prescaler, as well as the dynamics of tracking injection phase perturbations in injection-locked masterslave oscillators; demonstrating its versatility in application to any nonharmonic oscillator

다이렉트 경로를 이용한 5/8GHz 듀얼 모드 All-Digital Phase-Locked Loop의 설계

학위논문 (석사)-- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2019. 2. 정덕균.최근 데이터의 전송 속도가 비약적으로 증가함에 따라 데이터 처리 방식이 다양하게 연구되었고 여러 방식에 따른 고속의 송수신기 설계가 중요시되고 있다. 그 중에서도 Clock 신호를 합성하는 역할인 Phase-Locked Loop (PLL)에 대한 연구가 활발히 진행되고 있다. 특히 패시브 소자를 Loop Filter에 사용해야 하는 Analog PLL보다는 PVT 변화에 둔감하고 Programmable 하다는 장점을 가진 All Digital PLL (AD-PLL)에 대한 관심도가 높아지고 있다. 본 논문에서는 Peripheral Component Interconnect Express Memory interface (PCIe) 지원을 위한 32Gbps Serial Link에 Common Clock 신호를 제공하는 5/8 GHz 듀얼 모드 AD-PLL을 제안한다. 이전 세대와의 호환성을 위해 넓은 동작 영역을 갖고 모드 선택이 가능한 듀얼 모드 Digitally Controlled Oscillator (DCO)를 사용하였고 설계 전 Digital 방식으로 변환함에 따라 발생하는 Quantization Noise에 대해 분석하고 Matlab, Verilog Behavioral Simulation을 통해 출력의 Phase Noise와 RMS Jitter 값을 예측해 볼 수 있었다. 또한 Reference Clock의 한 주기 이내에 정보가 Update되지 못하는 Loop Delay의 문제를 해결하기 위해 Digital Loop Filter (DLF)의 처리 과정을 거치지 않고 Time to Digital Converter (TDC)의 출력을 DCO에 바로 전달해 줄 수 있는 다이렉트 경로를 제안하였다. 설계된 회로는 TSMC 사의 65nm 공정으로 구현되었고 AD-PLL의 전체 유효 면적은 Decoupling Cap을 제외하고 420um·300um이며 측정된 출력 Clock 신호의 RMS Jitter값은 8GHz 모드에서 357fs, 5GHz 모드에서 394fs이다. AD-PLL의 동작 주파수는 PCIe Spec의 다양한 모드를 지원하기 위해 외부의 입력 모드 신호에 따라서 5GHz/8GHz의 High/Low Band를 지원하고 1.2V의 공급 전압에서 Repeater를 제외하고 8GHz 모드에서는 총 18.26mW, 5GHz 모드에서는 총 12.06mW의 Power를 소비한다.As data transmission speed has increased in recent years, a variety of data processing techniques have been studied and high-speed transceiver has become important. Above all, Phase-Locked Loop (PLL), which synthesizes high frequency clock signal, is one of the important parts. In particular, All-Digital PLL(AD-PLL), which has advantage of programmability and PVT tolerance, is replacing Analog PLL that requires passive element utilization. This thesis presents a 5/8GHz dual mode AD-PLL to provide common clock signal to 32Gbps serial link to support Peripheral Component Interconnect Express(PCIe) PHY. For compatibility with previous generations and wide operating region, AD-PLL uses dual mode Digitally Controlled Oscillator(DCO). Before an actual design, output RMS Jitter, Phase Noise of AD-PLL and quantization error resulting from digital conversion are calculated and analyzed by using Matlab, Verilog behavioral simulation in a short time. In addition, the output of Time-to-Digital Converter(TDC) is directly delivered to the DCO without Digital Loop Filter(DLF) using direct path to solve loop delay issue where information cant be updated within a cycle of reference clock. The proposed AD-PLL is fabricated in 65nm CMOS process and effective area of AD-PLL is 420um·300um and the measured RMS Jitter is 357fs at 8GHz mode, 394fs at 5GHz mode. Also, proposed AD-PLL supports the low/high band(5/8GHz) to be compatible with the various modes of PCIe spec. Power dissipation is 18.26mW at 8GHz mode, 12.06mW at 5GHz mode in 1.2V supply voltage domain excluding repeater.제 1 장 서 론 1 1.1 연구의 배경 1 1.2 논문의 구성 3 제 2 장 Basics of AD-PLL 4 2.1 Introduction of AD-PLL 4 2.2 Building Blocks of AD-PLL 5 2.2.1 Time to Digital Converter 6 2.2.2 Digital Loop Filter 8 2.2.3 Digitally Controlled Oscillator 10 2.3 Phase Noise Analysis 13 2.4 Loop Delay 18 제 3 장 Design of AD-PLL 22 3.1 Design Consideration 22 3.2 Overall Architecture 22 3.3 Phase Frequency Detectable TDC 24 3.4 Digital Loop Filter 27 3.5 Digitally Controlled Oscillator 30 3.6 Direct Path 33 3.7 Level Shifter and Divider 36 3.8 Clock Tree 39 제 4 장 Measurement and Simulation Results 41 4.1 Measurement Setup 41 4.2 Die Photomicrograph 43 4.3 Frequency Tracking Behavior 44 4.4 Clock Distribution 46 4.5 Phase Noise and Spur 47 4.6 Performance Summary 53 제 5 장 Conclusion 55 참고 문헌 56 Abstract 59Maste

Design of Digital FMCW Chirp Synthesizer PLLs Using Continuous-Time Delta-Sigma Time-to-Digital Converters

Radar applications for driver assistance systems and autonomous vehicles have spurred the development of frequency-modulated continuous-wave (FMCW) radar. Continuous signal transmission and high operation frequencies in the K- and W-bands enable radar systems with low power consumption and small form factors. The radar performance depends on high-quality signal sources for chirp generation to ensure accurate and reliable target detection, requiring chirp synthesizers that offer fast frequency settling and low phase noise. Fractional-N phase locked loops (PLLs) are an effective tool for synthesis of FMCW waveform profiles, and advances in CMOS technology have enabled high-performance single-chip CMOS synthesizers for FMCW radar. Design approaches for FMCW chirp synthesizer PLLs need to address the conflicting requirements of fast settling and low close-in phase noise. While integrated PLLs can be implemented as analog or digital PLLs, analog PLLs still dominate for high frequencies. Digital PLLs offer greater programmability and area efficiency than their analog counterparts, but rely on high-resolution time-to-digital converters (TDCs) for low close-in phase noise. Performance limitations of conventional TDCs remain a roadblock for achieving low phase noise with high-frequency digital PLLs. This shortcoming of digital PLLs becomes even more pronounced with wide loop bandwidths as required for FMCW radar. To address this problem, this work presents digital FMCW chirp synthesizer PLLs using continuous-time delta-sigma TDCs. After a discussion of the requirements for PLL-based FMCW chirp synthesizers, this dissertation focuses on digital fractional-N PLL designs based on noise-shaping TDCs that leverage state-of-the-art delta-sigma modulator techniques to achieve low close-in phase noise in wide-bandwidth digital PLLs. First, an analysis of the PLL bandwidth and chirp linearity studies the design requirements for chirp synthesizer PLLs. Based on a model of a complete radar system, the analysis examines the impact of the PLL bandwidth on the radar performance. The modeling approach allows for a straightforward study of the radar accuracy and reliability as functions of the chirp parameters and the PLL configuration. Next, an 18-to-22GHz chirp synthesizer PLL that produces a 25-segment chirp for a 240GHz FMCW radar application is described. This synthesizer design adapts an existing third-order noise-shaping TDC design. A 65nm CMOS prototype achieves a measured close-in phase noise of -88dBc/Hz at 100kHz offset for wide PLL bandwidths and consumes 39.6mW. The prototype drives a radar testbed to demonstrate the effectiveness of the synthesizer design in a complete radar system. Finally, a second-order noise-shaping TDC based on a fourth-order bandpass delta-sigma modulator is introduced. This bandpass delta-sigma TDC leverages the high resolution of a bandpass delta-sigma modulator by sampling a sinusoidal PLL reference and applies digital down-conversion to achieve low TDC noise in the frequency band of interest. Based on the bandpass delta-sigma TDC, a 38GHz digital FMCW chirp synthesizer PLL is designed. The feedback divider applies phase interpolation with a phase rotation scheme to ensure the effectiveness of the low TDC noise. A prototype PLL, fabricated in 40nm CMOS, achieves a measured close-in phase noise of -85dBc/Hz at 100kHz offset for wide loop bandwidths >1MHz and consumes 68mW. It effectively generates fast (500MHz/55us) and precise (824kHz rms frequency error) triangular chirps for FMCW radar. The bandpass delta-sigma TDC achieves a measured integrated rms noise of 325fs in a 1MHz bandwidth.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147732/1/dweyer_1.pdfDescription of dweyer_1.pdf : Restricted to UM users only

Clocking and Skew-Optimization For Source-Synchronous Simultaneous Bidirectional Links

There is continuous expansion of computing capabilities in mobile devices which demands higher I/O bandwidth and dense parallel links supporting higher data rates. Highspeed signaling leverages technology advancements to achieve higher data rates but is limited by the bandwidth of the electrical copper channel which have not scaled accordingly. To meet the continuous data-rate demand, Simultaneous Bi-directional (SBD) signaling technique is an attractive alternative relative to uni-directional signaling as it can work at lower clock speeds, exhibits better spectral efficiency and provides higher throughput in pad limited PCBs. For low-power and more robust system, the SBD transceiver should utilize forwarded clock system and per-pin de-skew circuits to correct the phase difference developed between the data and clock. The system can be configured in two roles, master and slave. To save more power, the system should have only one clock generator. The master has its own clock source and shares its clock to the slave through the clock channel, and the slave uses this forwarded clock to deserialize the inbound data and serialize the outbound data. A clock-to-data skew exists which can be corrected with a phase tracking CDR. This thesis presents a low-power implementation of forwarded clocking and clock-to-data skew optimization for a 40 Gbps SBD transceiver. The design is implemented in 28nm CMOS technology and consumes 8.8mW of power for 20 Gbps NRZ data at 0.9 V supply. The area occupied by the clocking 0.018 mm^2 area

RF Frontend for Spectrum Analysis in Cognitive Radio

Advances in wireless technology have sparked a plethora of mobile communication standards to support a variety of applications. FCC predicts a looming crisis due to the exponentially growing demand for spectrum and it recommends to increase the efficiency of spectrum utilization. Cognitive Radio (CR) is envisioned as a radio technology which detects and exploits empty spectrum to improve the quality of communication. Spectrum analyzer for detecting spectrum holes is a key component required for implementing cognitive radio. Mitola's vision of using an RF Analog-to-Digital (ADC) to digitize the entire spectrum is not yet a reality. The traditional spectrum analysis technique based on a RF Front end using an LO Sweep is too slow, making it unsuitable to track fast hopping signals. In this work, we demonstrate an RF Frontend that can simplify the ADC's requirement by splitting the input spectrum into multiple channels. It avoids the problem of PLL settling by incorporating LO synthesis within the signal path using a concept called Iterative Down Converter. An example 0.75GHz-11.25GHz RF Channelizer is designed in 65nm Standard CMOS Process. The channelizer splits the input spectrum (10.5GHz bandwidth) into seven channels (each of bandwidth 1.5GHz). The channelizer shows the ability to rapidly switch from one channel to another (within a few ns) as well as down-converting multiple channels simultaneously (concurrency). The channelizer achieves a dynamic range of 54dB for a bandwidth of 10.5GHz, while consuming 540mW of power. Harmonic rejection mixer plays a key role in a broadband receiver. A novel order scalable harmonic rejection mixer architecture is described in this research. A proof-of-principle prototype has been designed and fabricated in a 45nm SOI technology. Experimental results demonstrate an operation range of 0.5GHz to 1.5GHz for the LO frequency while offering harmonic rejection better than 55dB for the 3rd harmonic and 58dB for the 5th harmonic across LO frequencies. While cognitive radio solves the spectrum efficiency problem in frequency domain, the electronic beam steering provides a spatial domain solution. Electronic beam forming using phased arrays have been claimed to improve spectrum efficiency by serving more number of users for a given bandwidth. A LO path phase-shifter with frequency-doubling is demonstrated for WiMAX applications

RF Frontend for Spectrum Analysis in Cognitive Radio

Advances in wireless technology have sparked a plethora of mobile communication standards to support a variety of applications. FCC predicts a looming crisis due to the exponentially growing demand for spectrum and it recommends to increase the efficiency of spectrum utilization. Cognitive Radio (CR) is envisioned as a radio technology which detects and exploits empty spectrum to improve the quality of communication. Spectrum analyzer for detecting spectrum holes is a key component required for implementing cognitive radio. Mitola's vision of using an RF Analog-to-Digital (ADC) to digitize the entire spectrum is not yet a reality. The traditional spectrum analysis technique based on a RF Front end using an LO Sweep is too slow, making it unsuitable to track fast hopping signals. In this work, we demonstrate an RF Frontend that can simplify the ADC's requirement by splitting the input spectrum into multiple channels. It avoids the problem of PLL settling by incorporating LO synthesis within the signal path using a concept called Iterative Down Converter. An example 0.75GHz-11.25GHz RF Channelizer is designed in 65nm Standard CMOS Process. The channelizer splits the input spectrum (10.5GHz bandwidth) into seven channels (each of bandwidth 1.5GHz). The channelizer shows the ability to rapidly switch from one channel to another (within a few ns) as well as down-converting multiple channels simultaneously (concurrency). The channelizer achieves a dynamic range of 54dB for a bandwidth of 10.5GHz, while consuming 540mW of power. Harmonic rejection mixer plays a key role in a broadband receiver. A novel order scalable harmonic rejection mixer architecture is described in this research. A proof-of-principle prototype has been designed and fabricated in a 45nm SOI technology. Experimental results demonstrate an operation range of 0.5GHz to 1.5GHz for the LO frequency while offering harmonic rejection better than 55dB for the 3rd harmonic and 58dB for the 5th harmonic across LO frequencies. While cognitive radio solves the spectrum efficiency problem in frequency domain, the electronic beam steering provides a spatial domain solution. Electronic beam forming using phased arrays have been claimed to improve spectrum efficiency by serving more number of users for a given bandwidth. A LO path phase-shifter with frequency-doubling is demonstrated for WiMAX applications

A high speed serializer/deserializer design

A Serializer/Deserializer (SerDes) is a circuit that converts parallel data into a serial stream and vice versa. It helps solve clock/data skew problems, simplifies data transmission, lowers the power consumption and reduces the chip cost. The goal of this project was to solve the challenges in high speed SerDes design, which included the low jitter design, wide bandwidth design and low power design. A quarter-rate multiplexer/demultiplexer (MUX/DEMUX) was implemented. This quarter-rate structure decreases the required clock frequency from one half to one quarter of the data rate. It is shown that this significantly relaxes the design of the VCO at high speed and achieves lower power consumption. A novel multi-phase LC-ring oscillator was developed to supply a low noise clock to the SerDes. This proposed VCO combined an LC-tank with a ring structure to achieve both wide tuning range (11%) and low phase noise (-110dBc/Hz at 1MHz offset). With this structure, a data rate of 36 Gb/s was realized with a measured peak-to-peak jitter of 10ps using 0.18microm SiGe BiCMOS technology. The power consumption is 3.6W with 3.4V power supply voltage. At a 60 Gb/s data rate the simulated peak-to-peak jitter was 4.8ps using 65nm CMOS technology. The power consumption is 92mW with 2V power supply voltage. A time-to-digital (TDC) calibration circuit was designed to compensate for the phase mismatches among the multiple phases of the PLL clock using a three dimensional fully depleted silicon on insulator (3D FDSOI) CMOS process. The 3D process separated the analog PLL portion from the digital calibration portion into different tiers. This eliminated the noise coupling through the common substrate in the 2D process. Mismatches caused by the vertical tier-to-tier interconnections and the temperature influence in the 3D process were attenuated by the proposed calibration circuit. The design strategy and circuits developed from this dissertation provide significant benefit to both wired and wireless applications