154 research outputs found
High Performance Integrated Circuit Blocks for High-IF Wideband Receivers
Due to the demand for highâperformance radio frequency (RF) integrated circuit
design in the past years, a systemâonâchip (SoC) that enables integration of analog and
digital parts on the same die has become the trend of the microelectronics industry. As
a result, a major requirement of the next generation of wireless devices is to support
multiple standards in the same chipâset. This would enable a single device to support
multiple peripheral applications and services.
Based on the aforementioned, the traditional superheterodyne frontâend
architecture is not suitable for such applications as it would require a complete receiver
for each standard to be supported. A more attractive alternative is the highintermediate
frequency (IF) radio architecture. In this case the signal is digitalized at an
intermediate frequency such as 200MHz. As a consequence, the baseband operations,
such as downâconversion and channel filtering, become more power and area efficient
in the digital domain. Such architecture releases the specifications for most of the frontâend building blocks, but the linearity and dynamic range of the ADC become the
bottlenecks in this system. The requirements of large bandwidth, high frequency and
enough resolution make such ADC very difficult to realize. Many ADC architectures
were analyzed and ContinuousâTime Bandpass SigmaâDelta (CTâBPâÎŁÎ) architecture was
found to be the most suitable solution in the highâIF receiver architecture since they
combine oversampling and noise shaping to get fairly high resolution in a limited
bandwidth.
A major issue in continuousâtime networks is the lack of accuracy due to powervoltageâ
temperature (PVT) tolerances that lead to over 20% pole variations compared
to their discreteâtime counterparts. An optimally tuned BP ÎŁÎ ADC requires correcting
for center frequency deviations, excess loop delay, and DAC coefficients. Due to these
undesirable effects, a calibration algorithm is necessary to compensate for these
variations in order to achieve high SNR requirements as technology shrinks.
In this work, a novel linearization technique for a Wideband LowâNoise
Amplifier (LNA) targeted for a frequency range of 3â7GHz is presented. Postâlayout
simulations show NF of 6.3dB, peak S21 of 6.1dB, and peak IIP3 of 21.3dBm,
respectively. The power consumption of the LNA is 5.8mA from 2V.
Secondly, the design of a CMOS 6th order CT BPâÎŁÎ modulator running at 800
MHz for HighâIF conversion of 10MHz bandwidth signals at 200 MHz is presented. A
novel transconductance amplifier has been developed to achieve high linearity and high
dynamic range at high frequencies. A 2âbit quantizer with offset cancellation is alsopresented. The sixthâorder modulator is implemented using 0.18 um TSMC standard
analog CMOS technology. Postâlayout simulations in cadence demonstrate that the
modulator achieves a SNDR of 78 dB (~13 bit) performance over a 14MHz bandwidth.
The modulatorâs static power consumption is 107mW from a supply power of ± 0.9V.
Finally, a calibration technique for the optimization of the Noise Transfer
Function CT BP ÎŁÎ modulators is presented. The proposed technique employs two test
tones applied at the input of the quantizer to evaluate the noise transfer function of
the ADC, using the capabilities of the Digital Signal Processing (DSP) platform usually
available in mixedâmode systems. Once the ADC output bit stream is captured,
necessary information to generate the control signals to tune the ADC parameters for
best SignalâtoâQuantization Noise Ratio (SQNR) performance is extracted via Leastâ
Mean Squared (LMS) softwareâbased algorithm. Since the two tones are located
outside the band of interest, the proposed global calibration approach can be used
online with no significant effect on the inâband content
Efficient Design and Synthesis of Decimation Filters for Wideband Delta-Sigma ADCs
A design methodology for synthesizing power-optimized decimation filters for wideband Delta Sigma (ÎÎŁ) analog-to-digital converters (ADCs) for next-generation wireless standards is presented. The decimation filter is designed to filter the out-of-band quantization noise from a fifth-order continuous-time ÎÎŁ modulator, with 20 MHz signal bandwidth and 14-bits resolution. The modulator employs an oversampling ratio (OSR) of 16 with a clock rate of 640 MHz. Retiming, pipelining, Canonical Signed Digits (CSD) encoding has been utilized along with an optimized halfband filter to realize the power savings in the overall decimation filter. A process flow to rapidly design the optimized filters in MATLAB, generate the hardware description language (HDL) code and then automatically synthesize the design using standard cells has been presented. The decimation filter is implemented using standard cells in a 45 nm CMOS technology occupies a layout area of 0.12 mm2 and consumes 8 mW power from the 1.1 V supply
Multi-stage noise shaping (MASH) delta-sigma modulators for wideband and multi-standard applications
Imperial Users onl
Design of a wideband low-power continuous-time sigma-delta (ÎŁÎ) analog-to-digital converter (ADC) in 90nm CMOS technology
The growing trend in VLSI systems is to shift more signal processing functionality from analog to digital domain to reduce manufacturing cost and improve reliability. It has resulted in the demand for wideband high-resolution analog-to-digital converters (ADCs). There are many different techniques for doing analog-to-digital conversions. Oversampling ADC based on sigma-delta (ÎŁÎ) modulation is receiving a lot of attention due to its significantly relaxed matching requirements on analog components. Moreover, it does not need a steep roll-off anti-aliasing filter. A ÎŁÎ ADC can be implemented either as a discrete time system or a continuous time one. Nowadays growing interest is focused on the continuous-time ÎŁÎ ADC for its use in the wideband and low-power applications, such as medical imaging, portable ultrasound systems, wireless receivers, and test equipments. A continuous-time ÎŁÎ ADC offers some important advantages over its discrete-time counterpart, including higher sampling frequency, intrinsic anti-alias filtering, much relaxed sampling network requirements, and low-voltage implementation. Especially it has the potential in achieving low power consumption.
This dissertation presents a novel fifth-order continuous-time ÎŁÎ ADC which is implemented in a 90nm CMOS technology with single 1.0-V power supply. To speed up design process, an improved direct design method is proposed and used to design the loop filter transfer function. To maximize the in-band gain provided by the loop filter, thus maximizing in-band noise suppression, the excess loop delay must be kept minimum. In this design, a very low latency 4-bit flash quantizer with digital-to-analog (DAC) trimming is utilized. DAC trimming technique is used to correct the quantizer offset error, which allows minimum-sized transistors to be used for fast and low-power operation. The modulator has sampling clock of 800MHz. It achieves a dynamic range (DR) of 75dB and a signal-to-noise-and-distortion ratio (SNDR) of 70dB over 25MHz input signal bandwidth with 16.4mW power dissipation. Our work is among the most improved published to date. It uses the lowest supply voltage and has the highest input signal bandwidth while dissipating the lowest power among the bandwidths exceeding 15MHz
Delta-Sigma Digitization and Optical Coherent Transmission of DOCSIS 3.1 Signals in Hybrid Fiber Coax Networks
We first demonstrate delta-sigma digitization and coherent transmission of data over cable system interface specification (DOCSIS) 3.1 signals in a hybrid fiber coax (HFC) network. Twenty 192-MHz DOCSIS 3.1 channels with modulation up to 16384QAM are digitized by a low-pass cascade resonator feedback (CRFB) delta-sigma analog-to-digital converter (ADC) and transmitted over 80 km fiber using coherent single-λ 128-Gb/s dual-polarization (DP)-QPSK and 256-Gb/s DP-16QAM optical links. Both one-bit and two-bit delta-sigma digitization are implemented and supported by the QPSK and 16QAM coherent transmission systems, respectively. To facilitate its practical application in access networks, the coherent system is built using a low-cost narrowband optical modulator and RF amplifiers. Modulation error ratio (MER) larger than 50 dB is successfully demonstrated for all 20 DOCSIS 3.1 channels, and high order modulation up to 16384QAM is delivered over fiber for the first time in HFC networks. The raw DOCSIS data capacity is 54 Gb/s with net user information ~45 Gb/s. Moreover, the bit error ratio (BER) tolerance is evaluated by measuring the MER performance as BER increases. Negligible MER degradation is observed for BER up to 1.5 Ă 10â6 and 1.7 Ă 10â4, for one-bit and two-bit digitization, respectively
High Performance Integrated Circuit Blocks for High-IF Wideband Receivers
Due to the demand for highâperformance radio frequency (RF) integrated circuit
design in the past years, a systemâonâchip (SoC) that enables integration of analog and
digital parts on the same die has become the trend of the microelectronics industry. As
a result, a major requirement of the next generation of wireless devices is to support
multiple standards in the same chipâset. This would enable a single device to support
multiple peripheral applications and services.
Based on the aforementioned, the traditional superheterodyne frontâend
architecture is not suitable for such applications as it would require a complete receiver
for each standard to be supported. A more attractive alternative is the highintermediate
frequency (IF) radio architecture. In this case the signal is digitalized at an
intermediate frequency such as 200MHz. As a consequence, the baseband operations,
such as downâconversion and channel filtering, become more power and area efficient
in the digital domain. Such architecture releases the specifications for most of the frontâend building blocks, but the linearity and dynamic range of the ADC become the
bottlenecks in this system. The requirements of large bandwidth, high frequency and
enough resolution make such ADC very difficult to realize. Many ADC architectures
were analyzed and ContinuousâTime Bandpass SigmaâDelta (CTâBPâÎŁÎ) architecture was
found to be the most suitable solution in the highâIF receiver architecture since they
combine oversampling and noise shaping to get fairly high resolution in a limited
bandwidth.
A major issue in continuousâtime networks is the lack of accuracy due to powervoltageâ
temperature (PVT) tolerances that lead to over 20% pole variations compared
to their discreteâtime counterparts. An optimally tuned BP ÎŁÎ ADC requires correcting
for center frequency deviations, excess loop delay, and DAC coefficients. Due to these
undesirable effects, a calibration algorithm is necessary to compensate for these
variations in order to achieve high SNR requirements as technology shrinks.
In this work, a novel linearization technique for a Wideband LowâNoise
Amplifier (LNA) targeted for a frequency range of 3â7GHz is presented. Postâlayout
simulations show NF of 6.3dB, peak S21 of 6.1dB, and peak IIP3 of 21.3dBm,
respectively. The power consumption of the LNA is 5.8mA from 2V.
Secondly, the design of a CMOS 6th order CT BPâÎŁÎ modulator running at 800
MHz for HighâIF conversion of 10MHz bandwidth signals at 200 MHz is presented. A
novel transconductance amplifier has been developed to achieve high linearity and high
dynamic range at high frequencies. A 2âbit quantizer with offset cancellation is alsopresented. The sixthâorder modulator is implemented using 0.18 um TSMC standard
analog CMOS technology. Postâlayout simulations in cadence demonstrate that the
modulator achieves a SNDR of 78 dB (~13 bit) performance over a 14MHz bandwidth.
The modulatorâs static power consumption is 107mW from a supply power of ± 0.9V.
Finally, a calibration technique for the optimization of the Noise Transfer
Function CT BP ÎŁÎ modulators is presented. The proposed technique employs two test
tones applied at the input of the quantizer to evaluate the noise transfer function of
the ADC, using the capabilities of the Digital Signal Processing (DSP) platform usually
available in mixedâmode systems. Once the ADC output bit stream is captured,
necessary information to generate the control signals to tune the ADC parameters for
best SignalâtoâQuantization Noise Ratio (SQNR) performance is extracted via Leastâ
Mean Squared (LMS) softwareâbased algorithm. Since the two tones are located
outside the band of interest, the proposed global calibration approach can be used
online with no significant effect on the inâband content
Error Correction For Automotive Telematics Systems
One benefit of data communication over the voice channel of the cellular network is to reliably transmit real-time high priority data in case of life critical situations. An important implementation of this use-case is the pan-European eCall automotive standard, which has already been deployed since 2018. This is the first international standard for mobile emergency call that was adopted by multiple regions in Europe and the world. Other countries in the world are currently working on deploying a similar emergency communication system, such as in Russia and China. Moreover, many experiments and road tests are conducted yearly to validate and improve the requirements of the system. The results have proven that the requirements are unachievable thus far, with a success rate of emergency data delivery of only 70%.
The eCall in-band modem transmits emergency information from the in-vehicle system (IVS) over the voice channel of the circuit switch real time communication system to the public safety answering point (PSAP) in case of a collision. The voice channel is characterized by the non-linear vocoder which is designed to compress speech waveforms. In addition, multipath fading, caused by the surrounding buildings and hills, results in severe signal distortion and causes delays in the transmission of the emergency information. Therefore, to reliably transmit data over the voice channels, the in-band modem modulates the data into speech-like (SL) waveforms, and employs a powerful forward error correcting (FEC) code to secure the real-time transmission.
In this dissertation, the Turbo coded performance of the eCall in-band modem is first evaluated through the adaptive white Gaussian noise (AWGN) channel and the adaptive multi-rate (AMR) voice channel. The modulation used is biorthogonal pulse position modulation (BPPM). Simulations are conducted for both the fast and robust eCall modem. The results show that the distortion added by the vocoder is significantly large and degrades the system performance. In addition, the robust modem performs better than the fast modem. For instance, to achieve a bit error rate (BER) of 10^{-6} using the AMR compression rate of 7.4 kbps, the signal-to-noise ratio (SNR) required is 5.5 dB for the robust modem while a SNR of 7.5 dB is required for the fast modem.
On the other hand, the fading effect is studied in the eCall channel. It was shown that the fading distribution does not follow a Rayleigh distribution. The performance of the in-band modem is evaluated through the AWGN, AMR and fading channel. The results are compared with a Rayleigh fading channel. The analysis shows that strong fading still exists in the voice channel after power control. The results explain the large delays and failure of the emergency data transmission to the PSAP. Thus, the eCall standard needs to re-evaluate their requirements in order to consider the impact of fading on the transmission of the modulated signals. The results can be directly applied to design real-time emergency communication systems, including modulation and coding
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