EKGNet: A 10.96{\mu}W Fully Analog Neural Network for Intra-Patient Arrhythmia Classification

We present an integrated approach by combining analog computing and deep learning for electrocardiogram (ECG) arrhythmia classification. We propose EKGNet, a hardware-efficient and fully analog arrhythmia classification architecture that archives high accuracy with low power consumption. The proposed architecture leverages the energy efficiency of transistors operating in the subthreshold region, eliminating the need for analog-to-digital converters (ADC) and static random access memory (SRAM). The system design includes a novel analog sequential Multiply-Accumulate (MAC) circuit that mitigates process, supply voltage, and temperature variations. Experimental evaluations on PhysioNet's MIT-BIH and PTB Diagnostics datasets demonstrate the effectiveness of the proposed method, achieving average balanced accuracy of 95% and 94.25% for intra-patient arrhythmia classification and myocardial infarction (MI) classification, respectively. This innovative approach presents a promising avenue for developing low-power arrhythmia classification systems with enhanced accuracy and transferability in biomedical applications.Comment: Accepted on IEEE Biomedical Circuits and Systems (BioCAS) 202

Low Power Personalized ECG Based System Design Methodology for Remote Cardiac Health Monitoring

This paper describes a mixed-signal ECG system for personalized and remote cardiac health monitoring. The novelty of this work is four-fold. Firstly, a low power analog front end with an efficient automatic gain control mechanism, maintaining the input of the ADC to a level rendering optimum SNR and the enhanced recyclic folded cascode opamp used as an integrator for ADC. Secondly, a novel on-the-fly PQRST Boundary Detection (BD) methodology is formulated for finding the boundaries in continuous ECG signal. Thirdly, a novel low-complexity ECG feature extraction architecture is designed by reusing the same module present in the proposed BD methodology. Fourthly, the system is having the capability to reconfigure the proposed Low power ADC for low (8 bits) and high (12 bits) resolution with the use of the feedback signal obtained from the digital block when it is in processing. The proposed system has been tested and validated on patient’s data from PTBDB, CSEDB and in-house IIT Hyderabad DB (IITHDB) and we have achieved an accuracy of 99% upon testing on various normal and abnormal ECG signals. The whole system is implemented in 180 nm technology resulting in 9.47W (@ 1 MHz) power consumption and occupying 1.74mm2 silicon area