InP DHBT Single-Stage and Multiplicative Distributed Amplifiers for Ultra-Wideband Amplification

This paper highlights the gain-bandwidth merit of the single stage distributed amplifier (SSDA) and its derivative multiplicative amplifier topologies (i.e. the cascaded SSDA (C-SSDA) and the matrix SSDA (M-SSDA)), for ultra-wideband amplification. Two new monolithic microwave integrated circuit (MMIC) amplifiers are presented: an SSDA MMIC with 7.1dB average gain and 200GHz bandwidth; and the world's first M-SSDA, which has a 12dB average gain and 170GHz bandwidth. Both amplifiers are based on an Indium Phosphide DHBT process with 250nm emitter width. To the authors best knowledge, the SSDA has the widest bandwidth for any single stage amplifier reported to date. Furthermore, the three tier M-SSDA has the highest bandwidth and gain-bandwidth product for any matrix amplifier reported to date

Distributed Circuit Analysis and Design for Ultra-wideband Communication and sub-mm Wave Applications

This thesis explores research into new distributed circuit design techniques and topologies, developed to extend the bandwidth of amplifiers operating in the mm and sub-mm wave regimes, and in optical and visible light communication systems. Theoretical, mathematical modelling and simulation-based studies are presented, with detailed designs of new circuits based on distributed amplifier (DA) principles, and constructed using a double heterojunction bipolar transistor (DHBT) indium phosphide (InP) process with fT =fmax of 350/600 GHz. A single stage DA (SSDA) with bandwidth of 345 GHz and 8 dB gain, based on novel techniques developed in this work, shows 140% bandwidth improvement over the conventional DA design. Furthermore, the matrix-single stage DA (M-SSDA) is proposed for higher gain than both the conventional DA and matrix amplifier. A two-tier M-SSDA with 14 dB gain at 300 GHz bandwidth, and a three-tier M-SSDA with a gain of 20 dB at 324 GHz bandwidth, based on a cascode gain cell and optimized for bandwidth and gain flatness, are presented based on full foundry simulation tests. Analytical and simulation-based studies of the noise performance peculiarities of the SSDA and its multiplicative derivatives are also presented. The newly proposed circuits are fabricated as monolithic microwave integrated circuits (MMICs), with measurements showing 7.1 dB gain and 200 GHz bandwidth for the SSDA and 12 dB gain at 170 GHz bandwidth for the three-tier M-SSDA. Details of layout, fabrication and testing; and discussion of performance limiting factors and layout optimization considerations are presented. Drawing on the concept of artificial transmission line synthesis in distributed amplification, a new technique to achieve up to three-fold improvement in the modulation bandwidth of light emitting diodes (LEDs) for visible light communication (VLC) is introduced. The thesis also describes the design and application of analogue pre-emphasis to improve signal-to-noise ratio in bandwidth limited optical transceivers

Integrated Antennas and Active Beamformers Technology for mm-Wave Phased-Array Systems

In this thesis, based on the indoor channel measurements and ray-tracing modeling for the indoor mm-wave wireless communications, the challenges of the design of the radio in this band is studied. Considering the recently developed standards such as IEEE 802.15.3c, ECMA and WiGig at 60 GHz, the link budget of the system design for different classes of operation is done and the requirement for the antenna and other RF sections are extracted. Based on radiation characteristics of mm-wave and the fundamental limits of low-cost Silicon technology, it is shown that phased-array is the ultimate solution for the radio and physical layer of the mobile millimeter wave multi-Gb/s wireless networks. Different phased-array configurations are studied and a low-cost single-receiver array architecture with RF phase-shifting is proposed. A systematic approach to the analysis of the overall noise-figure of the proposed architecture is presented and the component technical requirements are derived for the system level specifications. The proposed on-chip antennas and antenna-in-packages for various applications are designed and verified by the measurement results. The design of patch antennas on the low-cost RT/Duroid substrate and the slot antennas on the IPD technologies as well as the compact on-chip slot DRA antenna are explained in the antenna design section. The design of reflective-type phase shifters in CMOS and MEMS technologies is explained. Finally, the design details of two developed 60 GHz integrated phased-arrays in CMOS technology are discussed. Front-end circuit blocks such as LNA, continuous passive reflective-type phase shifters, power combiner and variable gain amplifiers are investigated, designed and developed for a 60 GHz phased-array radio in CMOS technology. In the first design, the two-element CMOS phased-array front-ends based on passive phase shifting architecture is proposed and developed. In the second phased-array, the recently developed on-chip dielectric resonator antenna in our group in lower frequency is scaled and integrated with the front-end

SiGe BiCMOS RF front-ends for adaptive wideband receivers

The pursuit of dense monolithic integration and higher operating speed continues to push the integrated circuit (IC) fabrication technologies to their limits. The increasing process variation, associated with aggressive technology scaling, is having a negative impact on circuit yield in current IC technologies, and the problem is likely to become worse in the future. Circuit solutions that are more tolerant of the process variations are needed to fully utilize the benefits of technology scaling. The primary goal of this research is to develop high-frequency circuits that can deliver consistent performance even under the threat of increasing process variation. These circuits can be used to build ``self-healing" systems, which can detect process imperfections and compensate accordingly to optimize performance. In addition to improving yield, such adaptive circuits and systems can provide more robust and efficient solutions for a wide range of applications under varying operational and environmental conditions.Silicon-germanium (SiGe) BiCMOS technology is an ideal platform for highly integrated systems requiring both high-performance analog and radio-frequency (RF) circuits as well as large-scale digital functionality. This research is focused on designing circuit components for a high-frequency wideband self-healing receiver in SiGe BiCMOS technology. An adaptive image-reject mixer, low insertion-loss switches, a wideband low-noise amplifier (LNA), and a SiGe complementary LC oscillator were designed. Healing algorithms were developed, and automated self-healing of multiple parameters of the mixer was demonstrated in measurement. A monte-carlo simulation based methodology was developed to verify the effectiveness of the healing procedure. In summary, this research developed circuits, algorithms, simulation tools, and methods that are useful for building "self-healing" systems.Ph.D

Millimeter-Wave Concurrent Dual-Band BiCMOS RFIC Front-End Module for Communication and Sensing Systems

This dissertation presents new circuit architectures and techniques for improving several key performances of BiCMOS RFIC building blocks that are used in wireless communication and sensing systems operating at millimeter-wave frequencies. The developed circuits and front-end module can be employed in concurrent dual-band transceivers for communication and sensing systems such as phased array and RFID systems. New 0.18-μm CMOS dual-bandpass filtering single-pole double-throw (SPDT) and transmit/receive (T/R) switches have been developed, and they operate in two different frequency bands centered at around 40 and 60 GHz (Design 1) and 24 and 60 GHz (Designs 2, 3 and 4). Design 1 is a concurrent dual-bandpass filtering T/R switch consisting of three SPDT switches based on a 3rd order band-pass filter with shunt nMOS transistors as the switching function. Design 2 is a 24/60-GHz concurrent dual-bandpass T/R switch consisting of dual-band λ/4 LC networks and resonators with shunt nMOS transistors as the switching function. Design 3 is a dual-band SPDT and T/R switches, which are capable of band-pass filtering as well as separate and concurrent switching operations in single/dual-band and transmission/reception. These components can act as diplexers with switching functions. Design 4 is a wideband concurrent dual-band SPDT switch with integrated dual-bandpass filtering, which is configured to make it approximately equivalent to a dual-band resonator in the on-state operation. A fully integrated 24/60-GHz concurrent dual-band LNA utilizing a dual-band LC circuit has been proposed. The LNA is based on a two-stage cascode topology with inductive degeneration. The dual-band LC circuit has the quarter-wavelength characteristic at two different frequencies, and it shows the dual pass-band and single stop-band characteristics when it is connected to the ground in shunt. Due to the cancellation of the stop-band signal and low-pass response by the LC circuit connected to the cascode nodes of the 1st and 2nd stages in the LNA, the LNA presents high stop-band rejection and good gain balance at 24 and 60 GHz. A concurrent dual-band front-end module (FEM) consisting of a 24/60-GHz dual-band antenna, a five-port T/R switch, two LNAs and one PA has been proposed. The FEM can be employed in systems with dual-polarization, for instance, phased array and RFID reader systems

Reconfigurable Load-Modulated Power Amplifier For Energy- and Spectrum-Efficient Wireless Communications

With the increasing demand for faster date rates and extensive user connectivities, the complex modulation schemes and large-scaled arrays have been widely researched and employed in the modern wireless links e.g., 5G and beyond-5G systems. These pose major challenges to design the power amplifiers (PAs) to accommodate the system level evolution. As the critical part, the power amplifiers (PAs) dominate the output power, efficiency, linearity and reliability of the radio frequency (RF) transmitter. Consequently, the PA\u27s capability of maintaining an efficient, linear and reliable signal amplification operation is essential to the communication systems. On the other hand, due to the deployment of massive multiple input/multiple output (MIMO) technique, the highly integrated active antenna systems replaced traditional 50Ω-based PA with sectorized antenna architectures. This brings the fact that, as the beam is steered in the antenna array, the dynamic load impedance observed from PAs can be up to 2: 1 Voltage Standing Wave Ratio (VSWR) due to the time-varying phasing and output power between the adjacent antenna elements and PAs, thus severely deteriorate PAs\u27 performance. To resolve aforementioned challenges, a novel design theory of Quasi-balanced Doherty power amplifier (QB-DPA) is first presented in this dissertation, which opens a new vision to counteract the mismatch-induced degradation using reconfigurable PA architectures. In this QB-DPA design, the isolation port of the PA\u27s output coupler is alternatively terminated to 50-Ω load and ground to enable the balanced and Doherty modes. With the implementation of the silicon-on-insulator (SOI)-based single-pole-double-throw (SPDT) switch to realize the reconfiguration, the physical prototype is demonstrated exhibiting remarkable DPA performance, in terms of the linearity, efficiency and output power. Subsequently, a series/parallel QB-DPA theory that not only can improve the back-off efficiency of QB-DPA, but also significantly restore the load-mismatch degradation is proposed. This novel topology includes and unifies QB-DPA modes at balanced, series and parallel Doherty, respectively. Moreover, a novel linearity-enhanced combiner is introduced for nominal 50-Ω load to improve the linearity at both series and parallel QB-DPA modes. The reconfiguration between series and parallel operations largely restore the performance degradation when the PAs suffer a dynamic antenna mismatch condition. Finally, a wideband mismatch-resilient QB-DPA is presented. Through parallel/series reconfiguration and reciprocal biasing, it is for the first time shown that the QB-DPA is able to maintain a stable output power as well as enhanced efficiency and linearity across 2 : 1 VSWR circle, and this operation can be seamlessly extended to a wide bandwidth which holds promising potential for application to array-based massive MIMO systems

Architectural Alternatives to Implement High-Performance Delta-Sigma Modulators

RÉSUMÉ Le besoin d’appareils portatifs, de téléphones intelligents et de systèmes microélectroniques implantables médicaux s’accroît remarquablement. Cependant, l’optimisation de l’alimentation de tous ces appareils électroniques portables est l’un des principaux défis en raison du manque de piles à grande capacité utilisées pour les alimenter. C’est un fait bien établi que le convertisseur analogique-numérique (CAN) est l’un des blocs les plus critiques de ces appareils et qu’il doit convertir efficacement les signaux analogiques au monde numérique pour effectuer un post-traitement tel que l’extraction de caractéristiques. Parmi les différents types de CAN, les modulateurs Delta Sigma (��M) ont été utilisés dans ces appareils en raison des fonctionnalités alléchantes qu’ils offrent. En raison du suréchantillonnage et pour éloigner le bruit de la bande d’intérêt, un CAN haute résolution peut être obtenu avec les architectures ��. Il offre également un compromis entre la fréquence d’échantillonnage et la résolution, tout en offrant une architecture programmable pour réaliser un CAN flexible. Ces CAN peuvent être implémentés avec des blocs analogiques de faible précision. De plus, ils peuvent être efficacement optimisés au niveau de l’architecture et circuits correspondants. Cette dernière caractéristique a été une motivation pour proposer différentes architectures au fil des ans. Cette thèse contribue à ce sujet en explorant de nouvelles architectures pour optimiser la structure ��M en termes de résolution, de consommation d’énergie et de surface de silicium. Des soucis particuliers doivent également être pris en compte pour faciliter la mise en œuvre du ��M. D’autre part, les nouveaux procédés CMOS de conception et fabrication apportent des améliorations remarquables en termes de vitesse, de taille et de consommation d’énergie lors de la mise en œuvre de circuits numériques. Une telle mise à l’échelle agressive des procédés, rend la conception de blocs analogiques tel que un amplificateur de transconductance opérationnel (OTA), difficile. Par conséquent, des soins spéciaux sont également pris en compte dans cette thèse pour surmonter les problèmes énumérés. Ayant mentionné ci-dessus que cette thèse est principalement composée de deux parties principales. La première concerne les nouvelles architectures implémentées en mode de tension et la seconde partie contient une nouvelle architecture réalisée en mode hybride tension et temps.----------ABSTRACT The need for hand-held devices, smart-phones and medical implantable microelectronic sys-tems, is remarkably growing up. However, keeping all these electronic devices power optimized is one of the main challenges due to the lack of long life-time batteries utilized to power them up. It is a well-established fact that analog-to-digital converter (ADC) is one of the most critical building blocks of such devices and it needs to efficiently convert analog signals to the digital world to perform post processing such as channelizing, feature extraction, etc. Among various type of ADCs, Delta Sigma Modulators (��Ms) have been widely used in those devices due to the tempting features they offer. In fact, due to oversampling and noise-shaping technique a high-resolution ADC can be achieved with �� architectures. It also offers a compromise between sampling frequency and resolution while providing a highly-programmable approach to realize an ADC. Moreover, such ADCs can be implemented with low-precision analog blocks. Last but not the least, they are capable of being effectively power optimized at both architectural and circuit levels. The latter has been a motivation to proposed different architectures over the years.This thesis contributes to this topic by exploring new architectures to effectively optimize the ��M structure in terms of resolution, power consumption and chip area. Special cares must also be taken into account to ease the implementation of the ��M. On the other hand, advanced node CMOS processes bring remarkable improvements in terms of speed, size and power consumption while implementing digital circuits. Such an aggressive process scaling, however, make the design of analog blocks, e.g. operational transconductance amplifiers (OTAs), cumbersome. Therefore, special cares are also taken into account in this thesis to overcome the mentioned issues. Having had above mentioned discussion, this thesis is mainly split in two main categories. First category addresses new architectures implemented in a pure voltage domain and the second category contains new architecture realized in a hybrid voltage and time domain. In doing so, the thesis first focuses on a switched-capacitor implementation of a ��M while presenting an architectural solution to overcome the limitations of the previous approaches. This limitations include a power hungry adder in a conventional feed-forward topology as well as power hungry OTAs

Transceiver architectures and sub-mW fast frequency-hopping synthesizers for ultra-low power WSNs

Wireless sensor networks (WSN) have the potential to become the third wireless revolution after wireless voice networks in the 80s and wireless data networks in the late 90s. This revolution will finally connect together the physical world of the human and the virtual world of the electronic devices. Though in the recent years large progress in power consumption reduction has been made in the wireless arena in order to increase the battery life, this is still not enough to achieve a wide adoption of this technology. Indeed, while nowadays consumers are used to charge batteries in laptops, mobile phones and other high-tech products, this operation becomes infeasible when scaled up to large industrial, enterprise or home networks composed of thousands of wireless nodes. Wireless sensor networks come as a new way to connect electronic equipments reducing, in this way, the costs associated with the installation and maintenance of large wired networks. To accomplish this task, it is necessary to reduce the energy consumption of the wireless node to a point where energy harvesting becomes feasible and the node energy autonomy exceeds the life time of the wireless node itself. This thesis focuses on the radio design, which is the backbone of any wireless node. A common approach to radio design for WSNs is to start from a very simple radio (like an RFID) adding more functionalities up to the point in which the power budget is reached. In this way, the robustness of the wireless link is traded off for power reducing the range of applications that can draw benefit form a WSN. In this thesis, we propose a novel approach to the radio design for WSNs. We started from a proven architecture like Bluetooth, and progressively we removed all the functionalities that are not required for WSNs. The robustness of the wireless link is guaranteed by using a fast frequency hopping spread spectrum technique while the power budget is achieved by optimizing the radio architecture and the frequency hopping synthesizer Two different radio architectures and a novel fast frequency hopping synthesizer are proposed that cover the large space of applications for WSNs. The two architectures make use of the peculiarities of each scenario and, together with a novel fast frequency hopping synthesizer, proved that spread spectrum techniques can be used also in severely power constrained scenarios like WSNs. This solution opens a new window toward a radio design, which ultimately trades off flexibility, rather than robustness, for power consumption. In this way, we broadened the range of applications for WSNs to areas in which security and reliability of the communication link are mandatory