Calibration of DAC mismatch errors in sigma delta ADCs based on a sine-wave measurement

We present an offline calibration procedure to correct the nonlinearity due element mismatch in the digital-to-analog converter (DAC) of a multibit Sigma Delta-modulation A/D converter. The calibration uses a single measurement on a sinusoidal input signal, from which the DAC errors can be estimated. The main quality of the calibration method is that it can be implemented completely in the digital domain (or in software) and does not intervene in any way in the analog modulator circuit. This way, the technique is a powerful tool for verifying and debugging designs. Due to the simplicity of the method, it may be also a viable approach for factory calibration

A 40MHz 12bit 84.2dB-SFDR continuous-time delta-sigma modulator in 90nm CMOS

A 4th-order 40MHz Bandwidth 12bit continuous-time delta-sigma modulator is presented in this paper. A shaped SC DAC with reduced peak current is proposed to relax the OTA slewing requirement, consuming no extra hardware or power. The DAC static and dynamic mismatches are eliminated by lookup table based digital calibration. With 1.2V supply and 69.6mW power in 90nm CMOS, the modulator achieves excellent SFDR of 84.2dB and 72.9dB peak SNDR at 960MHz clock frequency, corresponding to a FoM of 0.24pJ/Step. The core circuit area is about 0.28mm2