20 research outputs found
Advanced CMOS Integrated Circuit Design and Application
The recent development of various application systems and platforms, such as 5G, B5G, 6G, and IoT, is based on the advancement of CMOS integrated circuit (IC) technology that enables them to implement high-performance chipsets. In addition to development in the traditional fields of analog and digital integrated circuits, the development of CMOS IC design and application in high-power and high-frequency operations, which was previously thought to be possible only with compound semiconductor technology, is a core technology that drives rapid industrial development. This book aims to highlight advances in all aspects of CMOS integrated circuit design and applications without discriminating between different operating frequencies, output powers, and the analog/digital domains. Specific topics in the book include: Next-generation CMOS circuit design and application; CMOS RF/microwave/millimeter-wave/terahertz-wave integrated circuits and systems; CMOS integrated circuits specially used for wireless or wired systems and applications such as converters, sensors, interfaces, frequency synthesizers/generators/rectifiers, and so on; Algorithm and signal-processing methods to improve the performance of CMOS circuits and systems
Design of sigma-delta modulators for analog-to-digital conversion intensively using passive circuits
This thesis presents the analysis, design implementation and experimental evaluation of passiveactive discrete-time and continuous-time Sigma-Delta (ΣΔ) modulators (ΣΔMs) analog-todigital converters (ADCs).
Two prototype circuits were manufactured. The first one, a discrete-time 2nd-order ΣΔM, was designed in a 130 nm CMOS technology. This prototype confirmed the validity of the ultra incomplete settling (UIS) concept used for implementing the passive integrators. This circuit, clocked at 100 MHz and consuming 298 μW, achieves DR/SNR/SNDR of 78.2/73.9/72.8 dB, respectively, for a signal bandwidth of 300 kHz. This results in a Walden FoMW of 139.3 fJ/conv.-step and Schreier FoMS of 168 dB.
The final prototype circuit is a highly area and power efficient ΣΔM using a combination of a cascaded topology, a continuous-time RC loop filter and switched-capacitor feedback paths. The modulator requires only two low gain stages that are based on differential pairs. A systematic design methodology based on genetic algorithm, was used, which allowed decreasing the circuit’s sensitivity to the circuit components’ variations. This continuous-time, 2-1 MASH ΣΔM has been designed in a 65 nm CMOS technology and it occupies an area of just 0.027 mm2. Measurement results show that this modulator achieves a peak SNR/SNDR of 76/72.2 dB and DR of 77dB for an input signal bandwidth of 10 MHz, while dissipating 1.57 mW from a 1 V power supply voltage. The ΣΔM achieves a Walden FoMW of 23.6 fJ/level and a Schreier FoMS of 175 dB. The innovations proposed in this circuit result, both, in the reduction of the power consumption and of the chip size. To the best of the author’s knowledge the circuit achieves the lowest Walden FOMW for ΣΔMs operating at signal bandwidth from 5 MHz to 50 MHz reported to date
A 23μW Solar-Powered Keyword-Spotting ASIC with Ring-Oscillator-Based Time-Domain Feature Extraction
Voice-controlled interfaces on acoustic Internet-of-Things (IoT) sensor nodes and mobile devices require integrated low-power always-on wake-up functions such as Voice Activity Detection (VAD) and Keyword Spotting (KWS) to ensure longer battery life. Most VAD and KWS ICs focused on reducing the power of the feature extractor (FEx) as it is the most power-hungry building block. A serial Fast Fourier Transform (FFT)-based KWS chip [1] achieved 510nW; however, it suffered from a high 64ms latency and was limited to detection of only 1-to-4 keywords (2-to-5 classes). Although the analog FEx [2]–[3] for VAD/KWS reported 0.2μW-to-1 μW and 10ms-to-100ms latency, neither demonstrated >5 classes in keyword detection. In addition, their voltage-domain implementations cannot benefit from process scaling because the low supply voltage reduces signal swing; and the degradation of intrinsic gain forces transistors to have larger lengths and poor linearity
Nanopower CMOS transponders for UHF and microwave RFID systems
At first, we present an analysis and a discussion of the design options and tradeoffs for a passive microwave transponder. We derive a set of criteria for the optimization of the voltage multiplier, the power matching network and the backscatter modulator in order to optimize the operating range. In order to match the strictly power requirements, the communication protocol between transponder and reader has been chosen in a convenient way, in order to make the architecture of the passive transponder very simple and then ultra-low-power. From the circuital point of view, the digital section has been implemented in subthreshold CMOS logic with very low supply voltage and clock frequency. We present different solutions to supply power to the transponder, in order to keep the power consumption in the deep sub-µW regime and to drastically reduce the huge sensitivity of the subthreshold logic to temperature and process variations. Moreover, a low-voltage and low-power EEPROM in a standard CMOS process has been implemented. Finally, we have presented the implementation of the entire passive transponder, operating in the UHF or microwave frequency range
Robust Design With Increasing Device Variability In Sub-Micron Cmos And Beyond: A Bottom-Up Framework
My Ph.D. research develops a tiered systematic framework for designing process-independent and variability-tolerant integrated circuits. This bottom-up approach starts from designing self-compensated circuits as accurate building blocks, and moves up to sub-systems with negative feedback loop and full system-level calibration. a. Design methodology for self-compensated circuits My collaborators and I proposed a novel design methodology that offers designers intuitive insights to create new topologies that are self-compensated and intrinsically process-independent without external reference. It is the first systematic approaches to create "correct-by-design" low variation circuits, and can scale beyond sub-micron CMOS nodes and extend to emerging non-silicon nano-devices. We demonstrated this methodology with an addition-based current source in both 180nm and 90nm CMOS that has 2.5x improved process variation and 6.7x improved temperature sensitivity, and a GHz ring oscillator (RO) in 90nm CMOS with 65% reduction in frequency variation and 85ppm/oC temperature sensitivity. Compared to previous designs, our RO exhibits the lowest temperature sensitivity and process variation, while consuming the least amount of power in the GHz range. Another self-compensated low noise amplifiers (LNA) we designed also exhibits 3.5x improvement in both process and temperature variation and enhanced supply voltage regulation. As part of the efforts to improve the accuracy of the building blocks, I also demonstrated experimentally that due to "diversification effect", the upper bound of circuit accuracy can be better than the minimum tolerance of on-chip devices (MOSFET, R, C, and L), which allows circuit designers to achieve better accuracy with less chip area and power consumption. b. Negative feedback loop based sub-system I explored the feasibility of using high-accuracy DC blocks as low-variation "rulers-on-chip" to regulate high-speed high-variation blocks (e.g. GHz oscillators). In this way, the trade-off between speed (which can be translated to power) and variation can be effectively de-coupled. I demonstrated this proposed structure in an integrated GHz ring oscillators that achieve 2.6% frequency accuracy and 5x improved temperature sensitivity in 90nm CMOS. c. Power-efficient system-level calibration To enable full system-level calibration and further reduce power consumption in active feedback loops, I implemented a successive-approximation-based calibration scheme in a tunable GHz VCO for low power impulse radio in 65nm CMOS. Events such as power-up and temperature drifts are monitored by the circuits and used to trigger the need-based frequency calibration. With my proposed scheme and circuitry, the calibration can be performed under 135pJ and the oscillator can operate between 0.8 and 2GHz at merely 40[MICRO SIGN]W, which is ideal for extremely power-and-cost constraint applications such as implantable biomedical device and wireless sensor networks
Energy-Efficient Circuit Designs for Miniaturized Internet of Things and Wireless Neural Recording
Internet of Things (IoT) have become omnipresent over various territories including healthcare, smart building, agriculture, and environmental and industrial monitoring. Today, IoT are getting miniaturized, but at the same time, they are becoming more intelligent along with the explosive growth of machine learning. Not only do IoT sense and collect data and communicate,
but they also edge-compute and extract useful information within the small form factor. A main challenge of such miniaturized and intelligent IoT is to operate continuously for long lifetime within its low battery capacity. Energy efficiency of circuits and systems is key to addressing this challenge. This dissertation presents two different energy-efficient circuit designs: a 224pW 260ppm/°C gate-leakage-based timer for wireless sensor nodes (WSNs) for the IoT and an energy-efficient all analog machine learning accelerator with 1.2 µJ/inference of energy consumption for the CIFAR-10 and SVHN datasets.
Wireless neural interface is another area that demands miniaturized and energy-efficient circuits and systems for safe long-term monitoring of brain activity. Historically, implantable systems have used wires for data communication and power, increasing risks of tissue damage. Therefore, it has been a long-standing goal to distribute sub-mm-scale true floating and wireless implants throughout the brain and to record single-neuron-level activities. This dissertation presents a 0.19×0.17mm2 0.74µW wireless neural recording IC with near-infrared (NIR) power and data telemetry and a 0.19×0.28mm2 0.57µW light tolerant wireless neural recording IC.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/169712/1/jongyup_1.pd
Design of Low-Power Short-Distance Transceiver for Wireless Sensor Networks
Ph.DDOCTOR OF PHILOSOPH
Ultra-Low Power Transmitter and Power Management for Internet-of-Things Devices
Two of the most critical components in an Internet-of-Things (IoT) sensing and transmitting node are the power management unit (PMU) and the wireless transmitter (Tx). The desire for longer intervals between battery replacements or a completely self-contained, battery-less operation via energy harvesting transducers and circuits in IoT nodes demands highly efficient integrated circuits. This dissertation addresses the challenge of designing and implementing power management and Tx circuits with ultra-low power consumption to enable such efficient operation.
The first part of the dissertation focuses on the study and design of power management circuits for IoT nodes. This opening portion elaborates on two different areas of the power management field: Firstly, a low-complexity, SPICE-based model for general low dropout (LDO) regulators is demonstrated. The model aims to reduce the stress and computation times in the final stages of simulation and verification of Systems-on-Chip (SoC), including IoT nodes, that employ large numbers of LDOs. Secondly, the implementation of an efficient PMU for an energy harvesting system based on a thermoelectric generator transducer is discussed. The PMU includes a first-in-its-class LDO with programmable supply noise rejection for localized improvement in the suppression.
The second part of the dissertation addresses the challenge of designing an ultra-
low power wireless FSK Tx in the 900 MHz ISM band. To reduce the power consumption and boost the Tx energy efficiency, a novel delay cell exploiting current reuse is used in a ring-oscillator employed as the local oscillator generator scheme. In combination with an edge-combiner PA, the Tx showed a measured energy efficiency of 0.2 nJ/bit and a normalized energy efficiency of 3.1 nJ/(bit∙mW) when operating at output power levels up to -10 dBm and data rates of 3 Mbps. To close this dissertation, the implementation of a supply-noise tolerant BiCMOS ring-oscillator is discussed. The combination of a passive, high-pass feedforward path from the supply to critical nodes in the selected delay cell and a low cost LDO allow the oscillator to exhibit power supply noise rejection levels better than –33 dB in experimental results
의료용 인체 삽입물을 위한 무선 저전력 송수신기에 관한 연구
학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 2. 남상욱.This thesis presents the wireless transceiver for medical implant application. The high propagation loss in human body which has high relative permittivity and conductive makes the implantable device be required for high sensitivity. Moreover, the device should have low power consumption to use for wireless implant medical application due to a restricted battery life. Also, this problem should be solved for on-body device considering integration with mobile device in the future. Simultaneously, the specific medical application such as epiretinal prosthesis, multi-channel electroencephalogram sensor demand high-data rate. Therefore, it is a main challenge that enhancing the devices power consumption and data-rate for implantable medical application. In order to enhance the performance of the device, several techniques are proposed in implantable human body transceivers.
Firstly, the propagation loss in human-body is calculated for determine the frequency for medical implant application. The frequency bands allocated by FCC or MICS are too narrow and high lossy bands in human-body. For this reason, the optimum frequency for Implantable medical device is found by using Frisss formula and the link budget is calculated for capsule endoscopy system. The optimum frequency is verified through image recovery experiment in liquid human phantom and pig by using designed capsule endoscopy system.
Secondly, the Super-Regenerative Receiver (SRR) with Digital Self-Quenching Loop (DSQL) is proposed for low power consumption. The proposed DSQL replaces the envelope detector used in a conventional SRR and minimizes power consumption by generating a self-quench signal digitally for a super-regenerative oscillator. The measurement results are given to show the performance of the proposed receiver.
Thirdly, the RF Current Reused and Current Combining (CRCC) Power Amplifier (PA) is proposed for low power and high-speed transmitter. Normally, the PA having low output power has a feasibility issue that an optimum impedance of PA is too high to match with antenna impedance. For this reason, obtaining the maximum efficiency of PA is difficult for conventional structure. Moreover, conventional PAs output bandwidth is to be narrow due to high impedance transform ratio between PAs output and antennas input impedances. The CRCC structure solves this issue by decreasing the impedance transform ratio. The transmitter with CRCC PA is designed and verified through the measurement.Chapter 1. Introduction 1
1.1. WBAN (Wireless Body Area Network) 1
1.2. Challenges in Designing Transceiver for Medical Implant Application 7
Chapter 2. Propagation Loss in Human Body 10
2.1. Introduction 10
2.2. Far field approximation in human-body 13
2.3. Calculation of propagation loss in human-body 15
2.3.1. Frisss formula 15
2.3.2. Efficiency of transmitting antenna in human-body 17
2.4. Calculation of propagation loss in human-body and conclusion 19
Chapter 3. A Design of Transceiver for Capsule Endoscopy Application 21
3.1. Introduction 21
3.2. System Link Budget Calculation 24
3.3. Implementation 26
3.3.1. Transmitter with class B amplifier 26
3.3.2. Super-heterodyne receiver with AGC 28
3.3.3. Measurement results 30
3.4. Image recovery experiment 35
3.4.1. Integration of capsule endoscopy 35
3.4.2. Image recovery in the liquid human phantom 38
3.4.3. Image recovery in a pigs stomach and large intestine 40
3.5. Conclusion 41
Chapter 4. Super-Regenerative Receiver with Digitally Self-Quenching Loop 42
4.1. Introduction 42
4.1.1. Selection of receivers architecture for implantable medical device 44
4.1.2. Previous study of super-regenerative receiver 50
4.2. Main idea of proposed super-regenerative receiver 51
4.3. Description of proposed receiver 53
4.3.1. Digital self-quenching loop 55
4.3.2. Low noise amplifier and super-regenerative oscillator 57
4.3.3. Active RC filter for low power consumption 59
4.4. Experimental results 63
4.5. Summary and conclusion 69
Chapter 5. A Transmitter with Current-Reused and Current-Combining PA 71
5.1. Introduction 71
5.1.1. Previous study of OOK transmitter 72
5.2. Main idea of proposed transmitter 73
5.3. Description of proposed transmitter 79
5.3.1. Current-combining and current-reused PA 79
5.3.2. Ring oscillator with driving buffer 83
5.4. Experimental Results 85
5.5. Summary and conclusion 93
Chapter 6. Conclusion 95
Chapter 7. Appendix 97
7.1. Output spectrum of OOK signal 97
7.2. Theoretical BER of OOK comunication 99
Bibliography 101
초 록 109Docto