Low Power Analog to Digital Converters in Advanced CMOS Technology Nodes

The dissertation presents system and circuit solutions to improve the power efficiency and address high-speed design issues of ADCs in advanced CMOS technologies. For image sensor applications, a high-performance digitizer prototype based on column-parallel single-slope ADC (SS-ADC) topology for readout of a back-illuminated 3D-stacked CMOS image sensor is presented. To address the high power consumption issue in high-speed digital counters, a passing window (PW) based hybrid counter topology is proposed. To address the high column FPN under bright illumination conditions, a double auto-zeroing (AZ) scheme is proposed. The proposed techniques are experimentally verified in a prototype chip designed and fabricated in the TSMC 40 nm low-power CMOS process. The PW technique saves 52.8% of power consumption in the hybrid digital counters. Dark/bright column fixed pattern noise (FPN) of 0.0024%/0.028% is achieved employing the proposed double AZ technique for digital correlated double sampling (CDS). A single-column digitizer consumes total power of 66.8μW and occupies an area of 5.4 µm x 610 µm. For mobile/wireless receiver applications, this dissertation presents a low-power wide-bandwidth multistage noise-shaping (MASH) continuous-time delta-sigma modulator (CT-ΔΣM) employing finite impulse response (FIR) digital-to-analog converters (DACs) and encoder-embedded loop-unrolling (EELU) quantizers. The proposed MASH 1-1-1 topology is a cascade of three single-loop first-order CT-ΔΣM stages, each of which consists of an active-RC integrator, a current-steering DAC, and an EELU quantizer. An FIR filter in the main 1.5-bit DAC improves the modulator’s jitter sensitivity performance. FIR’s effect on the noise transfer function (NTF) of the modulator is compensated in the digital domain thanks to the MASH topology. Instead of employing a conventional analog direct feedback path, a 1.5-bit EELU quantizer based on multiplexing comparator outputs is proposed; this approach is suitable for highspeed operation together with power and area benefits. Fabricated in a 40-nm low-power CMOS technology, the modulator’s prototype achieves a 67.3 dB of signal-to-noise and distortion ratio (SNDR), 68 dB of signal-to-noise ratio (SNR), and 68.2 dB of dynamic range (DR) within 50.5 MHz of bandwidth (BW), while consuming 19 mW of total power (P). The proposed modulator features 161.5 dB of figure-of-merit (FOM), defined as FOM = SNDR + 10 log10 (BW/P)

A 77.3-dB SNDR 62.5-kHz Bandwidth Continuous-Time Noise-Shaping SAR ADC With Duty-Cycled G_m-C Integrator

This article presents a first-order continuous-time (CT) noise-shaping successive-approximation-register (NS-SAR) analog-to-digital converter (ADC). Different from other NS-SAR ADCs in literature, which are discrete-time (DT), this ADC utilizes a CT Gm-C integrator to realize an inherent anti-aliasing function. To cope with the timing conflict between the DT SAR ADC and the CT integrator, the sampling switch of the SAR ADC is removed, and the integrator is duty cycled to leave 5% of the sampling clock period for the SAR conversion. Redundancy is added to track the varying ADC input due to the absence of the sampling switch. A theoretical analysis shows that the 5% duty-cycling has negligible effects on the signal transfer function (STF) and the noise transfer function. The output swing and linearity requirements for the integrator are also relaxed thanks to the inherent feedforward path in the NS-SAR ADC architecture. Fabricated in 65-nm CMOS, the prototype achieves 77.3-dB peak signal-to-noise and distortion ratio (SNDR) in a 62.5-kHz bandwidth while consuming 13.5μ W, leading to a Schreier figure of merit (FoM) of 174.0 dB. Moreover, it provides 15-dB attenuation in the alias band.</p

Multi-Stage Noise-Shaping Continuous-Time Sigma-Delta Modulator

The design of a single-loop continuous-time ∑∆ modulator (CT∑∆M) with high resolution, wide bandwidth, and low power consumption is very challenging. The multi-stage noise-shaping (MASH) CT∑∆M architecture is identified as an advancement to the single-loop CT∑∆M architecture in order to satisfy the ever stringent requirements of next generation wireless systems. However, it suffers from the problems of quantization noise leakage and non-ideal interstage interfacing which hinder its widespread adoption. To solve these issues, this dissertation proposes a MASH CT∑∆M with on-chip RC time constant calibration circuits, multiple feedforward interstage paths, and a fully integrated noise cancellation filter (NCF). The prototype core modulator architecture is a cascade of two single-loop second- order CT∑∆M stages, each of which consists of an integrator-based active-RC loop filter, current-steering feedback digital-to-analog converters, and a four-bit flash quantizer. On-chip RC time constant calibration circuits and high gain multi-stage operational amplifiers are realized to mitigate quantization noise leakage due to process variation. Multiple feedforward interstage paths are introduced to (i) synthesize a fourth-order noise transfer function with DC zeros, (ii) simplify the design of NCF, and (iii) reduce signal swings at the second-stage integrator outputs. Fully integrated in 40 nm CMOS, the prototype chip achieves 74.4 dB of signal-to-noise and distortion ratio (SNDR), 75.8 dB of signal-to-noise ratio, and 76.8 dB of dynamic range in 50.3 MHz of bandwidth (BW) at 1 GHz of sampling frequency with 43.0 mW of power consumption (P). It does not require external software calibration and possesses minimal out-of-band signal transfer function peaking. The figure-of-merit (FOM), defined as FOM = SNDR + 10 log10(BW/P), is 165.1 dB

ダイナミック・アナログ回路を用いる高精度AD変換器の設計技術に関する研究

東京都市大学2018年度（平成30年

Analysis of single amplifier biquad based delta-sigma modulators

Continuous-time delta-sigma modulators (CT DSMs) are becoming a popular choice for high speed and high resolution applications. One of the challenges in their design is the loop filter power consumption, which increases with the modulator order. To alleviate this problem, single amplifier biquads (SABs) have been used. This report presents an analysis of finite gain, UGB effect and thermal noise of the biquads. Furthermore, an extension to the T network biquad is proposed for implementing a fourth order transfer function and is compared against the conventional architecture. The proposed topology requires only two OTAs to realize the transfer function. However, further analysis shows that the system becomes more sensitive to the finite UGB of the OTA.Electrical and Computer Engineerin