HIGH LINEARITY UNIVERSAL LNA DESIGNS FOR NEXT GENERATION WIRELESS APPLICATIONS

Design of the next generation (4G) systems is one of the most active and important area of research and development in wireless communications. The 2G and 3G technologies will still co-exist with the 4G for a certain period of time. Other applications such as wireless LAN (Local Area Network) and RFID are also widely used. As a result, there emerges a trend towards integrating multiple wireless functionalities into a single mobile device. Low noise amplifier (LNA), the most critical component of the receiver front-end, determines the sensitivity and noise figure of the receiver and is indispensable for the complete system. To satisfy the need for higher performance and diversity of wireless communication systems, three LNAs with different structures and techniques are proposed in the thesis based on the 4G applications. The first LNA is designed and optimized specifically for LTE applications, which could be easily added to the existing system to support different standards. In this cascode LNA, the nonlinearity coming from the common source (CS) and common gate (CG) stages are analyzed in detail, and a novel linear structure is proposed to enhance the linearity in a relatively wide bandwidth. The LNA has a bandwidth of 900MHz with the linearity of greater than 7.5dBm at the central frequency of 1.2GHz. Testing results show that the proposed structure effectively increases and maintains linearity of the LNA in a wide bandwidth. However, a broadband LNA that covers multiple frequency ranges appears more attractive due to system simplicity and low cost. The second design, a wideband LNA, is proposed to cover multiple wireless standards, such as LTE, RFID, GSM, and CDMA. A novel input-matching network is proposed to relax the tradeoff among noise figure and bandwidth. A high gain (>10dB) in a wide frequency range (1-3GHz) and a minimum NF of 2.5dB are achieved. The LNA consumes only 7mW on a 1.2V supply. The first and second LNAs are designed mainly for the LTE standard because it is the most widely used standard in the 4G communication systems. However, WiMAX, another 4G standard, is also being widely used in many applications. The third design targets on covering both the LTE and the WiMAX. An improved noise cancelling technique with gain enhancing structure is proposed in this design and the bandwidth is enlarged to 8GHz. In this frequency range, a maximum power gain of 14.5dB and a NF of 2.6-4.3dB are achieved. The core area of this LNA is 0.46x0.67mm2 and it consumes 17mW from a 1.2V supply. The three designs in the thesis work are proposed for the multi-standard applications based on the realization of the 4G technologies. The performance tradeoff among noise, linearity, and broadband impedance matching are explored and three new techniques are proposed for the tradeoff relaxation. The measurement results indicate the techniques effectively extend the bandwidth and suppress the increase of the NF and nonlinearity at high frequencies. The three proposed structures can be easily applied to the wideband and multi-standard LNA design

High frequency of low noise amplifier architecture for WiMAX application: A review

The low noise amplifier (LNA) circuit is exceptionally imperative as it promotes and initializes general execution performance and quality of the mobile communication system. LNA's design in radio frequency (R.F.) circuit requires the trade-off numerous imperative features' including gain, noise figure (N.F.), bandwidth, stability, sensitivity, power consumption, and complexity. Improvements to the LNA's overall performance should be made to fulfil the worldwide interoperability for microwave access (WiMAX) specifications' prerequisites. The development of front-end receiver, particularly the LNA, is genuinely pivotal for long-distance communications up to 50 km for a particular system with particular requirements. The LNA architecture has recently been designed to concentrate on a single transistor, cascode, or cascade constrained in gain, bandwidth, and noise figure

A Novel High Linearity and Low Power Folded CMOS LNA for UWB Receivers

© 2017 World Scientific Publishing Company. Electronic version of an article published as Journal of Circuits, Systems and Computers, Vol. 27, No. 03, 1850047, https://doi.org/10.1142/S0218126618500470.This paper presents a high linearity and low power Low-Noise Amplifier (LNA) for Ultra-Wideband (UWB) receivers based on CHRT 0.18μm CMOS technology. In this work, the folded topology is adopted in order to reduce the supply voltage and power consumption. Moreover, a band-pass LC filter is embedded in the folded-cascode circuit to extend bandwidth. The transconductance nonlinearity has a great impact on the whole LNA linearity performance under a low supply voltage. A post-distortion (PD) technique employing an auxiliary transistor is applied in the transconductance stage to improve the linearity. The post-layout simulation results indicate that the proposed LNA achieves a maximum power gain of 12.8dB. The input and output reflection coefficients both are lower than -10.0dB over 2.5~11.5GHz. The input third-order intercept point (IIP3) is 5.6dBm at 8GHz and the noise figure (NF) is lower than 4.0dB. The LNA consumes 5.4mW power under a 1V supply voltage.Peer reviewe

대역 외 방해신호에 내성을 가지는 광대역 수신기에 관한 연구

학위논문 (박사)-- 서울대학교 대학원 : 공과대학 전기·컴퓨터공학부, 2018. 2. 남상욱.In this thesis, a study of wideband receivers as one of the practical SDR receiver implementations is presented. The out-of-band interference signal (or blocker), which is the biggest problem of the wideband receiver is investigated, and have studied how to effectively remove it. As a result of reviewing previous studies, we have developed a wideband receiver based on the current-mode receiver structure and attempted to eliminate the blocker. The contents of the step-by-step research are as follows. First, attention was paid to the linearity of a low-noise transconductance amplifier (LNTA), which is the base block of current-mode receivers. In current-mode receivers, the LNTA should have a high transconductance (Gm) value to achieve a low noise figure, but a high Gm value results in low linearity. To solve this trade-off, we proposed a linearization method of transconductors. The proposed technique eliminates the third-order intermodulation distortion (IMD3) in a feed-forward manner using two paths. A transconductor having a transconductance of 2Gm is disposed in the main path, and an amplifier having a gain of ∛2 and a Gm-sized transconductor are located in the auxiliary path. This structure allows for some fundamental signal loss but cancel the IMD3 component at the output. As a result, the entire transconductor circuit can have high linearity due to the removed IMD3 component. We have designed a reconfigurable high-pass filter using a linearized transconductor and have demonstrated its performance. The fabricated circuit achieved a high input-referred third-order intercept point(IIP3) performance of 19.4 dBm. Then, a further improved linearized transconductor is designed. Since the linearized transconductors have a high noise figure due to the additional circuitry used for linearization, we have proposed a more suitable form for application to LNTA through noise figure analysis. The improved LNTA is designed to operate in low noise mode when there is no blocker, and can be switched to operate in high linearity mode when the blocker exists. We also applied noise cancelling techniques to the receiver to improve the noise figure performance of the wideband receiver circuit. A feedback path has been added to the current-mode receiver structure consisting of the LNTA, the mixer and the baseband transimpedance amplifier (TIA), and the noise signal can be detected using this path. This feedback path also maintains the input matching of the receiver to 50 Ω in a wide bandwidth. By adding an auxiliary path to the receiver, the in-band signal is amplified and the detected noise is removed from the baseband. The completed circuit exhibited wideband performance from 0.025 GHz to 2 GHz and IIP3 performance of -6.9 dBm in the high linearity mode. Finally, we designed a double noise-cancelling wideband receiver circuit by improving the performance of a wideband receiver with high immunity to blocker signals. In previous receivers, the LNTA was operated in two modes depending on the situation. In the improved receiver, the Gm ratio of the linearized LNTA was changed and the RF noise-cancelling technique was applied. The input matching and noise cancelling scheme introduced in the previous circuit was also applied and a wideband receiver circuit was designed to perform double noise-cancelling. As a result, the linearization and noise-cancellation of LNTA could be achieved at the same time, and the completed receiver circuit showed high IIP3 performance of 5 dBm with minimum noise figure of 1.4 dB. In conclusion, this thesis proposed a linearization technique for transconductor circuit and designed a wideband receiver based on current-mode receiver. The designed receiver circuit experimentally verified that it has low noise figure performance and high IIP3 performance and is tolerant to out-of-band blocker signals.Chapter 1. Introduction 1 1.1. Motivation of Wideband Receiver Architecture 2 1.2. Challenges in Designing Wideband Receiver 7 1.3. Prior Researches 13 1.3.1. N-Path Filter 14 1.3.2. Feed-Forward Blocker Filtering 16 1.3.3. Current-Mode Receiver 18 1.4. Research Objectives and Thesis Organization 22 Chapter 2. Transconductor Linearization Technique and Design of Tunable High-pass Filter 24 2.1. Transconductor Linearization Technique 27 2.2. Design of Tunable High-pass Filter 36 2.3. Measurement Results 41 2.4. Conclusions 46 Chapter 3. Wideband Noise-Cancelling Receiver Front-End Using Linearized Transconductor 47 3.1. Low-Noise Transconductance Amplifier Based on Linearized Transconductor 49 3.2. Wideband Noise-Cancelling Receiver Architecture 58 3.3. Measurement Results 64 3.4. Conclusions 70 Chapter 4. Blocker-Tolerant Wideband Double Noise-Cancelling Receiver Front-End 71 4.1. Linearized Noise-Cancelling Low-Noise Transconductance Amplifier 73 4.2. Wideband Double Noise-Cancelling Receiver Front-End 83 4.3. Measurement Results 90 4.4. Conclusions 97 Chapter 5. Conclusions 98 Bibliography 102 Abstract in Korean 112Docto

A Concurrent Dual-Band Inverter-Based Low Noise Amplifier (LNA) for WLAN Applications

low noise amplifier (LNA); concurrent; dual-band; inverter-basedIn this paper, a two-stage concurrent dual-band low noise amplifier (DB-LNA) operating at 2.4/5.2-GHz is presented for Wireless Local Area Network (WLAN) applications. The current-reused structure using resistive shunt-shunt feedback is employed to reduce power dissipation and achieve a wide frequency band from DC to-5.5-GHz in the inverter-based LNA. The second inverter-based stage is employed to increase the gain and obtain a flat gain over the frequency band. An LC network is also inserted at the proposed circuit output to shape the dual-band frequency response. The proposed concurrent DB-LNA is designed by RF-TSMC 0.18-µm CMOS technology, which consumes 10.8 mW from a power supply of 1.5 V. The simulation results show that the proposed DB-LNA achieves a direct power gain (S 21 ) of 13.7/14.1 dB, a noise figure (NF) of 4.2/4.6 dB, and an input return loss (S 11 ) of −12.9/−14.6 dBm at the 2.4/5.2-GHz bands

Microwave and Millimeter-wave Concurrent Multiband Low-Noise Amplifiers and Receiver Front-end in SiGe BiCMOS Technology

A fully integrated SiGe BiCMOS concurrent multiband receiver front-end and its building blocks including multiband low-noise amplifiers (LNAs), single-to-differential amplifiers and mixer are presented for various Ku-/K-/Ka-band applications. The proposed concurrent multiband receiver building blocks and receiver front-end achieve the best stopband rejection performances as compared to the existing multiband LNAs and receivers. First, a novel feedback tri-band load composed of two inductor feedback notch filters is proposed to overcome the low Q-factor of integrated passive inductors, and hence it provides superior stopband rejection ratio (SRR). A new 13.5/24/35-GHz concurrent tri-band LNA implementing the feedback tri-band load is presented. The developed tri-band LNA is the first concurrent tri-band LNA operating up to millimeter-wave region. By expanding the operating principle of the feedback tri-band load, a 21.5/36.5-GHz concurrent dual-band LNA with an inductor feedback dual-band load and another 23/36-GHz concurrent dual-band LNA with a new transformer feedback dual-band load are also presented. The latter provides more degrees of freedom for the creation of the stopband and passbands as compared to the former. A 22/36-GHz concurrent dual-band single-to-differential LNA employing a novel single-to-differential transformer feedback dual-band load is presented. The developed LNA is the first true concurrent dual-band single-to-differential amplifier. A novel 24.5/36.5 GHz concurrent dual-band merged single-to-differential LNA and mixer implementing the proposed single-to-differential transformer feedback dual-band load is also presented. With a 21-GHz LO signal, the down-converted dual IF bands are located at 3.5/15.5 GHz for two passband signals at 24.5/36.5 GHz, respectively. The proposed merged LNA and mixer is the first fully integrated concurrent dual-band mixer operating up to millimeter-wave frequencies without using any switching mechanism. Finally, a 24.5/36.5-GHz concurrent dual-band receiver front-end is proposed. It consists of the developed concurrent dual-band LNA using the single-to-single transformer feedback dual-band load and the developed concurrent dual-band merged LNA and mixer employing the single-to-differential transformer feedback dual-band load. The developed concurrent dual-band receiver front-end achieves the highest gain and the best NF performances with the largest SRRs, while operating at highest frequencies up to millimeter-wave region, among the concurrent dual-band receivers reported to date

Microwave and Millimeter-wave Concurrent Multiband Low-Noise Amplifiers and Receiver Front-end in SiGe BiCMOS Technology

A fully integrated SiGe BiCMOS concurrent multiband receiver front-end and its building blocks including multiband low-noise amplifiers (LNAs), single-to-differential amplifiers and mixer are presented for various Ku-/K-/Ka-band applications. The proposed concurrent multiband receiver building blocks and receiver front-end achieve the best stopband rejection performances as compared to the existing multiband LNAs and receivers. First, a novel feedback tri-band load composed of two inductor feedback notch filters is proposed to overcome the low Q-factor of integrated passive inductors, and hence it provides superior stopband rejection ratio (SRR). A new 13.5/24/35-GHz concurrent tri-band LNA implementing the feedback tri-band load is presented. The developed tri-band LNA is the first concurrent tri-band LNA operating up to millimeter-wave region. By expanding the operating principle of the feedback tri-band load, a 21.5/36.5-GHz concurrent dual-band LNA with an inductor feedback dual-band load and another 23/36-GHz concurrent dual-band LNA with a new transformer feedback dual-band load are also presented. The latter provides more degrees of freedom for the creation of the stopband and passbands as compared to the former. A 22/36-GHz concurrent dual-band single-to-differential LNA employing a novel single-to-differential transformer feedback dual-band load is presented. The developed LNA is the first true concurrent dual-band single-to-differential amplifier. A novel 24.5/36.5 GHz concurrent dual-band merged single-to-differential LNA and mixer implementing the proposed single-to-differential transformer feedback dual-band load is also presented. With a 21-GHz LO signal, the down-converted dual IF bands are located at 3.5/15.5 GHz for two passband signals at 24.5/36.5 GHz, respectively. The proposed merged LNA and mixer is the first fully integrated concurrent dual-band mixer operating up to millimeter-wave frequencies without using any switching mechanism. Finally, a 24.5/36.5-GHz concurrent dual-band receiver front-end is proposed. It consists of the developed concurrent dual-band LNA using the single-to-single transformer feedback dual-band load and the developed concurrent dual-band merged LNA and mixer employing the single-to-differential transformer feedback dual-band load. The developed concurrent dual-band receiver front-end achieves the highest gain and the best NF performances with the largest SRRs, while operating at highest frequencies up to millimeter-wave region, among the concurrent dual-band receivers reported to date

A Fully Integrated CMOS Receiver.

The rapidly growing wireless communication market is creating an increasing demand for low-cost highly-integrated radio frequency (RF) communication systems. This dissertation focuses on techniques to enable fully-integrated, wireless receivers incorporating all passive components, including the antenna, and also incorporating baseband synchronization on-chip. Not only is the receiver small in size and requires very low power, but it also delivers synchronized demodulated data. This research targets applications such as implantable neuroprosthetic devices and environmental wireless sensors, which need short range, low data-rate wireless communications but a long lifetime. To achieve these goals, the super-regenerative architecture is used, since power consumption with this architecture is low due to the simplified receiver architecture. This dissertation presents a 5GHz single chip receiver incorporating a compact on-chip 5 GHz slot antenna (50 times smaller than traditional dipole antennas) and a digital received data synchronization. A compact capacitively-loaded 5 GHz standing-wave resonator is used to improve the energy efficiency. An all-digital PLL timing scheme synchronizes the received data clock. A new type of low-power envelope detector is incorporated to increase the data rate and efficiency. The receiver achieves a data rate up to 1.2 Mb/s, dissipates 6.6 mW from a 1.5 V supply. The novel on-chip capacitively-loaded, transmission-line-standing-wave resonator is employed instead of a conventional low-Q on-chip inductor. The simulated quality factor of the resonator is very high (35), and is verified by phase-noise measurements of a prototype 5GHz Voltage Control Oscillator (VCO) incorporating this resonator. The prototype VCO, implemented in 0.13 µm CMOS, dissipates 3 mW from a 1.2 V supply, and achieves a measured phase noise of -117 dBc/Hz at a 1 MHz offset. In the on-chip antenna an efficient shielding technique is used to shield the antenna from the low-resistivity substrate underneath. Two standalone on-chip slot antenna prototypes were designed and fabricated in 0.13 µm CMOS. The 9 GHz prototype occupies a die area of only 0.3 mm2, has an active gain of -4.4 dBi and an efficiency of 9%. The second prototype occupies a die area of 0.47 mm2, and achieves a passive gain of approximately -17.0 dBi at 5 GHz.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/60739/1/shid_1.pd

Survey on individual components for a 5 GHz receiver system using 130 nm CMOS technology

La intención de esta tesis es recopilar información desde un punto de vista general sobre los diferentes tipos de componentes utilizados en un receptor de señales a 5 GHz utilizando tecnología CMOS. Se ha realizado una descripción y análisis de cada uno de los componentes que forman el sistema, destacando diferentes tipos de configuraciones, figuras de mérito y otros parámetros. Se muestra una tabla resumen al final de cada sección, comparando algunos diseños que se han ido presentando a lo largo de los años en conferencias internacionales de la IEEE.The intention of this thesis is to gather information from an overview point about the different types of components used in a 5 GHz receiver using CMOS technology. A review of each of the components that form the system has been made, highlighting different types of configurations, figure of merits and parameters. A summary table is shown at the end of each section, comparing many designs that have been presented over the years at international conferences of the IEEE.Departamento de Ingeniería Energética y FluidomecánicaGrado en Ingeniería en Electrónica Industrial y Automátic

Lna Ic Design For Cognitive Radio Implementation

This thesis presents a wideband inductorless three-stage common source (CS) low noise amplifier (LNA) with negative feedback for cognitive radio communication applications covering the range of 300 MHz to 10 GHz. Designed in Global Foundries’ 0.13 um CMOS process and through post-layout simulations over the covered band, the minimum and maximum voltage gain is 10 dB and 12.1 dB respectively whereas noise figure of 3.9 to 5.1 dB. S11 < -8.5 dB for the covered band and S11 < -10 dB is achieved up to 8.7 GHz. IIP3 achieves a minimum of -0.5dBm and maximum of 0.8 dBm at pre-layout simulations. The power consumption is 36 mW at 1.2 V. The LNA occupies an area of 26 μm × 46 μm excluding pads and 672 μm × 233 μm with pads