Comparator Design in Sensors for Environmental Monitoring

This paper presents circuit design considerations of comparator in analog-to-digital converters (ADC) applied for a portable, low-cost and high performance nano-sensor chip which can be applied to detect the airborne magnetite pollution nano particulate matter (PM) for environmental monitoring. High-resolution ADC plays a vital important role in high perfor-mance nano-sensor, while high-resolution comparator is a key component in ADC. In this work, some important design issues related to comparators in analog-to-digital converters (ADCs) are discussed, simulation results show that the resolution of the comparator proposed can achieve 5µV , and it is appropriate for high-resolution application

A Subthreshold SCL Based Pipelined Encoder for Ultra-Low Power 8-bit Folding/Interpolating ADC

The subthreshold MOS source-coupled logic (STSCL) technique is of great interest for designing ultra low power circuits. In this paper we discuss the design of a pipelined encoder for an 8-bit folding and interpolating (F&I) analog-to-digital (ADC) data converter using this technique. The encoder is designed and characterized in a conventional 0.18μm CMOS technology, and it is capable of operating over a wide frequency range (10kHz-50MHz) without the need of resizing the transistors or scaling the voltage levels. The speed and power consumption of the encoder are proportional to the bias currents of the gates. The supply voltage of the circuit can be as low as 350mV

Design and Simulation of SIGMA DELTA ADC

Analog-to-digital converters play an essential role in modern RF receiver design.Conventional Nyquist converters require analog components that are precise andHighly immune to noise and interference. In contrast, oversampling converters can be implemented using simple and high-tolerance analog components. Moreover,Sampling at high frequency eliminates the need for abrupt cutoffs in the analog antialiasing filters. A technique of noise shaping is used in Ó-Ä converters in addition to oversampling to achieve a high-resolution conversion. A significant advantage of the method is that analog signals are converted using simple and high-tolerance analog circuits, usually a 1-bit comparator, and analog signal processing circuits having a precision that is usually much less than the resolution of the overall converter. In this paper, the design technique for a low-cost first order narrow band sigma-delta modulator in a standard 0.9ìm CMOS technology is described .This circuitry performs the function of an analog-to-digital converter. A first-order 1-bit sigma-delta (Ó-Ä) analog-to-digital converter is designed and simulated using Cadence 0.9ìm CMOS process technology with power supply of 1.8 V through Cadence. The analysis of sigma-delta modulator structures and the design flow were given. The modulator is proved to be robustness, the high performance in stability .The simulation are compared with those from a traditional analog-to-digital converter to prove that sigma-delta is performing better in the case of weak signals acquisition. The design flow consist of a op-amp one of the key component of sigma delta adc which is used for designing of integrator and summing circuit , followed by a high speed comparator and a digital -to-analog convertor in the feedback path

Design and Simulation of an 8-Bit Successive Approximation Register Charge-Redistribution Analog-To-Digital Converter

The thesis initially investigates the history of the monolithic ADCs. The next chapter explores the different types of ADCs available in the market today. Next, the operation of a 4-bit SAR ADC has been studied. Based on this analysis, an 8-bit charge-redistribution SAR ADC has been designed and simulated with Multisim (National Instruments, Austin, TX). The design is divided into different blocks which are individually implemented and tested. Level-1 SPICE MOSFET models representative of 5μm devices were used wherever individual MOSFETs were used in the design. Finally, the power dissipation during the conversion period was also estimated. The supply voltage for the ADC is 5V and the clock frequency is 500KHz

Design and Implementation of a Novel Flash ADC for Ultra Wide Band Applications

This dissertation presents a design and implementation of a novel flash ADC architecture for ultra wide band applications. The advancement in wireless technology takes us in to a world without wires. Most of the wireless communication systems use digital signal processing to transmit as well as receive the information. The real world signals are analog. Due to the processing complexity of the analog signal, it is converted to digital form so that processing becomes easier. The development in the digital signal processor field is rapid due to the advancement in the integrated circuit technology over the last decade. Therefore, analog-to -digital converter acts as an interface in between analog signal and digital signal processing systems. The continuous speed enhancement of the wireless communication systems brings out huge demands in speed and power specifications of high-speed low-resolution analog-to -digital converters. Even though wired technology is a primary mode of communication, the quality and efficiency of the wireless technology allows us to apply to biomedical applications, in home services and even to radar applications. These applications are highly relying on wireless technology to send and receive information at high speed with great accuracy. Ultra Wideband (UWB) technology is the best method to these applications. A UWB signal has a bandwidth of minimum 500MHz or a fractional bandwidth of 25 percentage of its centre frequency. The two different technology standards that are used in UWB are multiband orthogonal frequency division multiplexing ultra wideband technology (MB-OFDM) and carrier free direct sequence ultra wideband technology (DS-UWB). ADC is the core of any UWB receiver. Generally a high speed flash ADC is used in DS-UWB receiver. Two different flash ADC architectures are proposed in this thesis for DS-UWB applications. The first design is a high speed five bit flash ADC architecture with a sampling rate of 5 GS/s. The design is verified using CADENCE tool with CMOS 90 nm technology. The total power dissipation of the ADC is 8.381 mW from power supply of 1.2 V. The die area of the proposed flash ADC is 186 μm × 210 μm (0.039 mm2). The proposed flash ADC is analysed and compared with other papers in the literature having same resolution and it is concluded that it has the highest speed of operation with medium power dissipation. iii The second design is a reconfigurable five bit flash ADC architecture with a sampling rate of 1.25 GS/s. The design is verified using CADENCE tool with UMC 180 nm technology. The total power dissipation of the ADC is 11.71 mW from power supply of 1.8 V. The die area of the implementation is 432 μm × 720 μm (0.31104 mm2). The chip tape out of the proposed reconfigurable flash ADC is made for fabrication

LOW- VOLTAGE HIGH EFFICIENCY ANALOG-TO-DIGITAL CONVERTER FOR BIOMEDICAL SENSOR INTERFACE

Ph.DDOCTOR OF PHILOSOPH

Fundamental Blocks for a 0.18um Cyclic Analog-to-Digital Converter

The goal of this project was to design a fully differential Cyclic Analog-to-Digital Converter, and test the functionality of its major blocks. The converter is an integrated circuit designed for the CMOS 0.18 micron fabrication process. It is self-calibrating and performs 1 million samples per second. Design techniques used include switched capacitor networks, differential amplifier, replica biasing, and calibration in the off-chip digital domain. The project is sponsored by the New England Center for Analog and Mixed Signal Design (NECAMSID)