A Phase Change Memory Chip Based on TiSbTe Alloy in 40-nm Standard CMOS Technology

In this letter, a phase change random access memory (PCRAM) chip based on Ti0.4Sb2Te3 alloy material was fabricated in a 40-nm 4-metal level complementary metal-oxide semiconductor (CMOS) technology. The phase change resistor was then integrated after CMOS logic fabrication. The PCRAM was successfully embedded without changing any logic device and process, in which 1.1 V negative-channel metal-oxide semiconductor device was used as the memory cell selector. The currents and the time of SET and RESET operations were found to be 0.2 and 0.5 mA, 100 and 10 ns, respectively. The high speed performance of this chip may highlight the design advantages in many embedded applications

Stochastic Memory Devices for Security and Computing

With the widespread use of mobile computing and internet of things, secured communication and chip authentication have become extremely important. Hardware-based security concepts generally provide the best performance in terms of a good standard of security, low power consumption, and large-area density. In these concepts, the stochastic properties of nanoscale devices, such as the physical and geometrical variations of the process, are harnessed for true random number generators (TRNGs) and physical unclonable functions (PUFs). Emerging memory devices, such as resistive-switching memory (RRAM), phase-change memory (PCM), and spin-transfer torque magnetic memory (STT-MRAM), rely on a unique combination of physical mechanisms for transport and switching, thus appear to be an ideal source of entropy for TRNGs and PUFs. An overview of stochastic phenomena in memory devices and their use for developing security and computing primitives is provided. First, a broad classification of methods to generate true random numbers via the stochastic properties of nanoscale devices is presented. Then, practical implementations of stochastic TRNGs, such as hardware security and stochastic computing, are shown. Finally, future challenges to stochastic memory development are discussed

Integrated Circuits/Microchips

With the world marching inexorably towards the fourth industrial revolution (IR 4.0), one is now embracing lives with artificial intelligence (AI), the Internet of Things (IoTs), virtual reality (VR) and 5G technology. Wherever we are, whatever we are doing, there are electronic devices that we rely indispensably on. While some of these technologies, such as those fueled with smart, autonomous systems, are seemingly precocious; others have existed for quite a while. These devices range from simple home appliances, entertainment media to complex aeronautical instruments. Clearly, the daily lives of mankind today are interwoven seamlessly with electronics. Surprising as it may seem, the cornerstone that empowers these electronic devices is nothing more than a mere diminutive semiconductor cube block. More colloquially referred to as the Very-Large-Scale-Integration (VLSI) chip or an integrated circuit (IC) chip or simply a microchip, this semiconductor cube block, approximately the size of a grain of rice, is composed of millions to billions of transistors. The transistors are interconnected in such a way that allows electrical circuitries for certain applications to be realized. Some of these chips serve specific permanent applications and are known as Application Specific Integrated Circuits (ASICS); while, others are computing processors which could be programmed for diverse applications. The computer processor, together with its supporting hardware and user interfaces, is known as an embedded system.In this book, a variety of topics related to microchips are extensively illustrated. The topics encompass the physics of the microchip device, as well as its design methods and applications

High-Density Solid-State Memory Devices and Technologies

This Special Issue aims to examine high-density solid-state memory devices and technologies from various standpoints in an attempt to foster their continuous success in the future. Considering that broadening of the range of applications will likely offer different types of solid-state memories their chance in the spotlight, the Special Issue is not focused on a specific storage solution but rather embraces all the most relevant solid-state memory devices and technologies currently on stage. Even the subjects dealt with in this Special Issue are widespread, ranging from process and design issues/innovations to the experimental and theoretical analysis of the operation and from the performance and reliability of memory devices and arrays to the exploitation of solid-state memories to pursue new computing paradigms

Towards integrating chalcogenide based phase change memory with silicon microelectronics

The continued dominance of floating gate technology as the premier non-volatile memory (NVM) technology is expected to hit a roadblock due to issues associated with its inability to catch up with CMOS scaling. The uncertain future of floating gate memory has led to a host of unorthodox NVM technologies to surface as potential heirs. Among the mix is phase change memory (PCM), which is a non-volatile, resistance variable, memory technology wherein the state of the memory bit is defined by the resistance of the memory material. This research study examines novel, bilayer chalcogenide based materials composed of Ge-chalcogenide (GeTe or Ge2Se3) and Sn-chalcogenide (SnTe or SnSe) for phase change memory applications and explores their integration with CMOS technology. By using a layered arrangement, it is possible to induce phase change response in materials, which normally do not exhibit such behavior, and thus form new materials which may have lower threshold voltage and programming current requirements. Also, through the incorporation of a metal containing layer, the phase transition characteristics of the memory layer can be tailored in order to obtain in-situ, a material with optimized phase change properties. Using X-ray diffraction (XRD) and time resolved XRD, it has been demonstrated that stacked phase change memory films exhibit both structural and compositional dependency with annealing temperature. The outcome of the structural transformation of the bottom layer, is an annealing temperature dependent residual stress. By the incorporation of a Sn layer, the phase transition characteristics of Ge-chalcogenide thin films can be tuned. Clear evidence of thermally induced Ge, Sn and chalcogen inter-diffusion, has been discerned via transmission electron microscopy and parallel electron energy loss spectroscopy. The presence of Al2O3 as capping layer has been found to mitigate volatilization and metallic Sn phase separation at high temperatures. Two terminal PCM cells employing these bilayers have been designed, fabricated and tested. All devices exhibit threshold switching and memory switching behavior. By the application of suitable voltage programming pulses, RESET state switching can be accomplished in these devices, thus demonstrating single bit memory functionality. A process for integrating bilayer PCM technology with 2 µm CMOS has been designed and developed. The baseline RIT CMOS process has been modified to incorporate 12 levels of photolithography, 3 levels of metal and the addition of PCM as a BEOL process. On electrical testing, NMOS connected PCM devices exhibit switching behavior. The effect of the state (SET/RESET) of the series connected PCM cell on the drain current of the NMOS has also been investigated. It is determined that threshold switching of the PCM cell is essential in order to observe any change in MOS drain current with variation in drain voltage. Thus, successful integration of bilayer PCM with CMOS has been demonstrated

Applications of memristors in conventional analogue electronics

This dissertation presents the steps employed to activate and utilise analogue memristive devices in conventional analogue circuits and beyond. TiO2 memristors are mainly utilised in this study, and their large variability in operation in between similar devices is identified. A specialised memristor characterisation instrument is designed and built to mitigate this issue and to allow access to large numbers of devices at a time. Its performance is quantified against linear resistors, crossbars of linear resistors, stand-alone memristive elements and crossbars of memristors. This platform allows for a wide range of different pulsing algorithms to be applied on individual devices, or on crossbars of memristive elements, and is used throughout this dissertation. Different ways of achieving analogue resistive switching from any device state are presented. Results of these are used to devise a state-of-art biasing parameter finder which automatically extracts pulsing parameters that induce repeatable analogue resistive switching. IV measurements taken during analogue resistive switching are then utilised to model the internal atomic structure of two devices, via fittings by the Simmons tunnelling barrier model. These reveal that voltage pulses modulate a nano-tunnelling gap along a conical shape. Further retention measurements are performed which reveal that under certain conditions, TiO2 memristors become volatile at short time scales. This volatile behaviour is then implemented into a novel SPICE volatile memristor model. These characterisation methods of solid-state devices allowed for inclusion of TiO2 memristors in practical electronic circuits. Firstly, in the context of large analogue resistive crossbars, a crosspoint reading method is analysed and improved via a 3-step technique. Its scaling performance is then quantified via SPICE simulations. Next, the observed volatile dynamics of memristors are exploited in two separate sequence detectors, with applications in neuromorphic engineering. Finally, the memristor as a programmable resistive weight is exploited to synthesise a memristive programmable gain amplifier and a practical memristive automatic gain control circuit.Open Acces