8 research outputs found
Advances in Solid State Circuit Technologies
This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields
Sistema de predicción epileptogenica en lazo cerrado basado en matrices sub-durales
The human brain is the most complex organ in the human body, which consists of
approximately 100 billion neurons. These cells effortlessly communicate over multiple
hemispheres to deliver our everyday sensorimotor and cognitive abilities.
Although the underlying principles of neuronal communication are not well understood,
there is evidence to suggest precise synchronisation and/or de-synchronisation
of neuronal clusters could play an important role. Furthermore, new evidence suggests
that these patterns of synchronisation could be used as an identifier for the detection
of a variety of neurological disorders including, Alzheimers (AD), Schizophrenia (SZ)
and Epilepsy (EP), where neural degradation or hyper synchronous networks have
been detected.
Over the years many different techniques have been proposed for the detection of
synchronisation patterns, in the form of spectral analysis, transform approaches and
statistical based studies. Nonetheless, most are confined to software based implementations
as opposed to hardware realisations due to their complexity. Furthermore, the
few hardware implementations which do exist, suffer from a lack of scalability, in terms
of brain area coverage, throughput and power consumption.
Here we introduce the design and implementation of a hardware efficient algorithm,
named Delay Difference Analysis (DDA), for the identification of patient specific
synchronisation patterns. The design is remarkably hardware friendly when compared
with other algorithms. In fact, we can reduce hardware requirements by as much as
80% and power consumption as much as 90%, when compared with the most common
techniques. In terms of absolute sensitivity the DDA produces an average sensitivity
of more than 80% for a false positive rate of 0.75 FP/h and indeed up to a maximum
of 90% for confidence levels of 95%. This thesis presents two integer-based digital processors for the calculation of
phase synchronisation between neural signals. It is based on the measurement of time
periods between two consecutive minima. The simplicity of the approach allows for
the use of elementary digital blocks, such as registers, counters or adders. In fact,
the first introduced processor was fabricated in a 0.18μm CMOS process and only
occupies 0.05mm2 and consumes 15nW from a 0.5V supply voltage at a signal input
rate of 1024S/s. These low-area and low-power features make the proposed circuit a
valuable computing element in closed-loop neural prosthesis for the treatment of neural
disorders, such as epilepsy, or for measuring functional connectivity maps between
different recording sites in the brain.
A second VLSI implementation was designed and integrated as a mass integrated
16-channel design. Incorporated into the design were 16 individual synchronisation
processors (15 on-line processors and 1 test processor) each with a dedicated training
and calculation module, used to build a specialised epileptic detection system based
on patient specific synchrony thresholds. Each of the main processors are capable of
calculating the phase synchrony between 9 independent electroencephalography (EEG)
signals over 8 epochs of time totalling 120 EEG combinations. Remarkably, the entire
circuit occupies a total area of only 3.64 mm2.
This design was implemented with a multi-purpose focus in mind. Firstly, as a
clinical aid to help physicians detect pathological brain states, where the small area
would allow the patient to wear the device for home trials. Moreover, the small power
consumption would allow to run from standard batteries for long periods. The trials
could produce important patient specific information which could be processed using
mathematical tools such as graph theory. Secondly, the design was focused towards the
use as an in-vivo device to detect phase synchrony in real time for patients who suffer
with such neurological disorders as EP, which need constant monitoring and feedback.
In future developments this synchronisation device would make an good contribution
to a full system on chip device for detection and stimulation.El cerebro humano es el órgano más complejo del cuerpo humano, que consta
de aproximadamente 100 mil millones de neuronas. Estas células se comunican sin
esfuerzo a través de ambos hemisferios para favorecer nuestras habilidades sensoriales
y cognitivas diarias.
Si bien los principios subyacentes de la comunicación neuronal no se comprenden
bien, existen pruebas que sugieren que la sincronización precisa y/o la desincronización
de los grupos neuronales podrían desempeñar un papel importante. Además, nuevas
evidencias sugieren que estos patrones de sincronización podrían usarse como un identificador
para la detección de una gran variedad de trastornos neurológicos incluyendo
la enfermedad de Alzheimer(AD), la esquizofrenia(SZ) y la epilepsia(EP), donde se ha
detectado la degradación neural o las redes hiper sincrónicas.
A lo largo de los años, se han propuesto muchas técnicas diferentes para la detección
de patrones de sincronización en forma de análisis espectral, enfoques de transformación
y análisis estadísticos. No obstante, la mayoría se limita a implementaciones basadas
en software en lugar de realizaciones de hardware debido a su complejidad. Además,
las pocas implementaciones de hardware que existen, sufren una falta de escalabilidad,
en términos de cobertura del área del cerebro, rendimiento y consumo de energía.
Aquí presentamos el diseño y la implementación de un algoritmo eficiente de
hardware llamado “Delay Difference Aproximation” (DDA) para la identificación
de patrones de sincronización específicos del paciente. El diseño es notablemente
compatible con el hardware en comparación con otros algoritmos. De hecho, podemos
reducir los requisitos de hardware hasta en un 80% y el consumo de energía hasta en
un 90%, en comparación con las técnicas más comunes. En términos de sensibilidad
absoluta, la DDA produce una sensibilidad promedio de más del 80% para una tasa de
falsos positivos de 0,75 PF / hr y hasta un máximo del 90% para niveles de confianza
del 95%.
Esta tesis presenta dos procesadores digitales para el cálculo de la sincronización de
fase entre señales neuronales. Se basa en la medición de los períodos de tiempo entre dos
mínimos consecutivos. La simplicidad del enfoque permite el uso de bloques digitales
elementales, como registros, contadores o sumadores. De hecho, el primer procesador
introducido se fabricó en un proceso CMOS de 0.18μm y solo ocupa 0.05mm2 y consume
15nW de un voltaje de suministro de 0.5V a una tasa de entrada de señal de 1024S/s Estas características de baja área y baja potencia hacen que el procesador propuesto
sea un valioso elemento informático en prótesis neurales de circuito cerrado para el
tratamiento de trastornos neuronales, como la epilepsia, o para medir mapas de
conectividad funcional entre diferentes sitios de registro en el cerebro.
Además, se diseñó una segunda implementación VLSI que se integró como un
diseño de 16 canales integrado en masa. Se incorporaron al diseño 16 procesadores
de sincronización individuales (15 procesadores en línea y 1 procesador de prueba),
cada uno con un módulo de entrenamiento y cálculo dedicado, utilizado para construir
un sistema de detección epiléptico especializado basado en umbrales de sincronía
específicos del paciente. Cada uno de los procesadores principales es capaz de calcular
la sincronización de fase entre 9 señales de electroencefalografía (EEG) independientes
en 8 épocas de tiempo que totalizan 120 combinaciones de EEG. Cabe destacar que
todo el circuito ocupa un área total de solo 3.64 mm2.
Este diseño fue implementado teniendo en mente varios propósitos. En primer
lugar, como ayuda clínica para ayudar a los médicos a detectar estados cerebrales
patológicos, donde el área pequeña permitiría al paciente usar el dispositivo para las
pruebas caseras. Además, el pequeño consumo de energía permitiría una carga cero del
dispositivo, lo que le permitiría funcionar con baterías estándar durante largos períodos.
Los ensayos podrían producir información importante específica para el paciente que
podría procesarse utilizando herramientas matemáticas como la teoría de grafos. En
segundo lugar, el diseño se centró en el uso como un dispositivo in-vivo para detectar la
sincronización de fase en tiempo real para pacientes que sufren trastornos neurológicos
como el EP, que necesitan supervisión y retroalimentación constantes. En desarrollos
futuros, este dispositivo de sincronización sería una buena base para desarrollar un
sistema completo de un dispositivo chip para detección de trastornos neurológicos
CMOS SPAD-based image sensor for single photon counting and time of flight imaging
The facility to capture the arrival of a single photon, is the fundamental limit to the detection of quantised
electromagnetic radiation. An image sensor capable of capturing a picture with this ultimate optical and
temporal precision is the pinnacle of photo-sensing. The creation of high spatial resolution, single photon
sensitive, and time-resolved image sensors in complementary metal oxide semiconductor (CMOS) technology
offers numerous benefits in a wide field of applications. These CMOS devices will be suitable to replace high
sensitivity charge-coupled device (CCD) technology (electron-multiplied or electron bombarded) with
significantly lower cost and comparable performance in low light or high speed scenarios. For example, with
temporal resolution in the order of nano and picoseconds, detailed three-dimensional (3D) pictures can be
formed by measuring the time of flight (TOF) of a light pulse. High frame rate imaging of single photons can
yield new capabilities in super-resolution microscopy. Also, the imaging of quantum effects such as the
entanglement of photons may be realised.
The goal of this research project is the development of such an image sensor by exploiting single photon
avalanche diodes (SPAD) in advanced imaging-specific 130nm front side illuminated (FSI) CMOS technology.
SPADs have three key combined advantages over other imaging technologies: single photon sensitivity,
picosecond temporal resolution and the facility to be integrated in standard CMOS technology. Analogue
techniques are employed to create an efficient and compact imager that is scalable to mega-pixel arrays. A
SPAD-based image sensor is described with 320 by 240 pixels at a pitch of 8μm and an optical efficiency or
fill-factor of 26.8%. Each pixel comprises a SPAD with a hybrid analogue counting and memory circuit that
makes novel use of a low-power charge transfer amplifier. Global shutter single photon counting images are
captured. These exhibit photon shot noise limited statistics with unprecedented low input-referred noise at an
equivalent of 0.06 electrons.
The CMOS image sensor (CIS) trends of shrinking pixels, increasing array sizes, decreasing read noise, fast
readout and oversampled image formation are projected towards the formation of binary single photon imagers
or quanta image sensors (QIS). In a binary digital image capture mode, the image sensor offers a look-ahead to
the properties and performance of future QISs with 20,000 binary frames per second readout with a bit error
rate of 1.7 x 10-3. The bit density, or cumulative binary intensity, against exposure performance of this image
sensor is in the shape of the famous Hurter and Driffield densitometry curves of photographic film.
Oversampled time-gated binary image capture is demonstrated, capturing 3D TOF images with 3.8cm
precision in a 60cm range
Primitives and design of the intelligent pixel multimedia communicator
Communication systems arc an ever more essential component of our modern global society. Mobile communications systems are still in a state of rapid advancement and growth. Technology is constantly evolving at a rapid pace in ever more diverse areas and the emerging mobile multimedia based communication systems offer new challenges for both current and future technologies. To realise the full potential of mobile multimedia communication systems there is a need to explore new options to solve some of the fundamental problems facing the technology. In particular, the complexity of such a system within an infrastructure framework that is inherently limited by its power sources and has very restricted transmission bandwidth demands new methodologies and approaches