3 research outputs found

    Infraestructura de càlcul HPC CIMNE

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    Projecte realitzat al CIMNE, Centre Internacional de Mètodes NumèricsL'objectiu d'aquest projecte és el de renovar integralment la infraestructura de càlcul del CIMNE determinant quins dels equipaments actuals es poden utilitzar, llavors implementant un nou sistema operatiu al clúster, aplicant un gestor de recursos i planificador de treballs centralitzat i eficaç, proporcionant una documentació completa tant pels usuaris com pels administradors juntament amb procediments estàndard de gestió, millorant la seguretat de tot el conjunt, implementant sistemes de monitorització, determinant alguna plataforma de comunicació i documentació entre usuaris i realitzant dos estudis, un referent a l'arquitectura del hardware i l'altre de consum i sostenibilitat, aspecte que no s'havia tingut en compte fins el plantejament d'aquest projecte

    Analisi delle principali piattaforme mobile ai fini del loro impiego per la gestione dell'assistenza clienti di una ditta informatica

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    Il seguente studio di fattibilità ha lo scopo di integrare features e funzionalità mobile ad un sistema informativo già realizzato ed implementato. L'introduzione dei terminali mobile di ultima generazione consente all'azienda committente dello studio di poter gestire, fruire, modificare, inserire, aggiornare i dati direttamente da remoto tramite device mobile quali smartphone, pda o palmari. Le soluzioni proposte analizzano varie configurazioni e piattaforma HW/SW quali Windows Mobile, Google Android, Apple iPhone, e parecchi software applicativi, dai gestionali rdbms per dispositivi mobile come HanDBase, Visual CE, abcDB, SprintDB Pro, a complessi ed articolati ambienti di sviluppo RAD come WINDEV Mobile, Mobiforms, ModelBaker con i quali sviluppare vere e proprie app per differenti piattaform

    Monolithic electronic-photonic integration in state-of-the-art CMOS processes

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    Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Cataloged from student submitted PDF version of thesis.Includes bibliographical references (p. 388-407).As silicon CMOS transistors have scaled, increasing the density and energy efficiency of computation on a single chip, the off-chip communication link to memory has emerged as the major bottleneck within modern processors. Photonic devices promise to break this bottleneck with superior bandwidth-density and energy-efficiency. Initial work by many research groups to adapt photonic device designs to a silicon-based material platform demonstrated suitable independent performance for such links. However, electronic-photonic integration attempts to date have been limited by the high cost and complexity associated with modifying CMOS platforms suitable for modern high-performance computing applications. In this work, we instead utilize existing state-of-the-art electronic CMOS processes to fabricate integrated photonics by: modifying designs to match the existing process; preparing a design-rule compliant layout within industry-standard CAD tools; and locally-removing the handle silicon substrate in the photonic region through post-processing. This effort has resulted in the fabrication of seven test chips from two major foundries in 28, 45, 65 and 90 nm CMOS processes. Of these efforts, a single die fabricated through a widely available 45nm SOI-CMOS mask-share foundry with integrated waveguides with 3.7 dB/cm propagation loss alongside unmodified electronics with less than 5 ps inverter stage delay serves as a proof-of-concept for this approach. Demonstrated photonic devices include high-extinction carrier-injection modulators, 8-channel wavelength division multiplexing filter banks and low-efficiency silicon germanium photodetectors. Simultaneous electronic-photonic functionality is verified by recording a 600 Mb/s eye diagram from a resonant modulator driven by integrated digital circuits. Initial work towards photonic device integration within the peripheral CMOS flow of a memory process that has resulted in polysilicon waveguide propagation losses of 6.4 dB/cm will also be presented.by Jason S. Orcutt.Ph.D
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