A FPGA/DSP design for real-time fracture detection using low transient pulse

This work presents the hardware and software architecture for the detection of fractures and edges in materials. While the detection method is based on the novel concept of Low Transient Pulse (LTP), the overall system implementation is based on two digital microelectronics technologies widely used for signal processing: Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA). Under the proposed architecture, the DSP carries out the analysis of the received baseband signal at a lower rate and hence can be used for large number of signal channels. The FPGA\u27s master clock runs at a higher frequency (62.5MHz) for the generation of LTP signal and to demodulate the passband ultrasonic signals sampled at 1MHz which interrupts the DSP at every 1 [Is. This research elaborates on designing a Quadrature Amplitude Modulator - demodulator (QAM) on the FPGA for the received signal from the ultrasound and edge detection on the DSP processor to detect the presence of edges/fractures on a test Sawbone plate. In this work, the LTP technology is applied to determine the location of the Sawbone plate edges based on the reflected signals to the receivers. This signal is then passed through a QAM to get the maxima (peaks) at the received signal to study the parameters in the DSP. This work successfully demonstrates the feasibility of modular programming approach across the two platforms. The dual time scale platform readily accommodates higher temporal resolution needed for the generation of Low Transient Pulses and the processing of real time baseband signals on the DSP for various test conditions

Bidirectional Neural Interface Circuits with On-Chip Stimulation Artifact Reduction Schemes

Bidirectional neural interfaces are tools designed to “communicate” with the brain via recording and modulation of neuronal activity. The bidirectional interface systems have been adopted for many applications. Neuroscientists employ them to map neuronal circuits through precise stimulation and recording. Medical doctors deploy them as adaptable medical devices which control therapeutic stimulation parameters based on monitoring real-time neural activity. Brain-machine-interface (BMI) researchers use neural interfaces to bypass the nervous system and directly control neuroprosthetics or brain-computer-interface (BCI) spellers. In bidirectional interfaces, the implantable transducers as well as the corresponding electronic circuits and systems face several challenges. A high channel count, low power consumption, and reduced system size are desirable for potential chronic deployment and wider applicability. Moreover, a neural interface designed for robust closed-loop operation requires the mitigation of stimulation artifacts which corrupt the recorded signals. This dissertation introduces several techniques targeting low power consumption, small size, and reduction of stimulation artifacts. These techniques are implemented for extracellular electrophysiological recording and two stimulation modalities: direct current stimulation for closed-loop control of seizure detection/quench and optical stimulation for optogenetic studies. While the two modalities differ in their mechanisms, hardware implementation, and applications, they share many crucial system-level challenges. The first method aims at solving the critical issue of stimulation artifacts saturating the preamplifier in the recording front-end. To prevent saturation, a novel mixed-signal stimulation artifact cancellation circuit is devised to subtract the artifact before amplification and maintain the standard input range of a power-hungry preamplifier. Additional novel techniques have been also implemented to lower the noise and power consumption. A common average referencing (CAR) front-end circuit eliminates the cross-channel common mode noise by averaging and subtracting it in analog domain. A range-adapting SAR ADC saves additional power by eliminating unnecessary conversion cycles when the input signal is small. Measurements of an integrated circuit (IC) prototype demonstrate the attenuation of stimulation artifacts by up to 42 dB and cross-channel noise suppression by up to 39.8 dB. The power consumption per channel is maintained at 330 nW, while the area per channel is only 0.17 mm2. The second system implements a compact headstage for closed-loop optogenetic stimulation and electrophysiological recording. This design targets a miniaturized form factor, high channel count, and high-precision stimulation control suitable for rodent in-vivo optogenetic studies. Monolithically integrated optoelectrodes (which include 12 µLEDs for optical stimulation and 12 electrical recording sites) are combined with an off-the-shelf recording IC and a custom-designed high-precision LED driver. 32 recording and 12 stimulation channels can be individually accessed and controlled on a small headstage with dimensions of 2.16 x 2.38 x 0.35 cm and mass of 1.9 g. A third system prototype improves the optogenetic headstage prototype by furthering system integration and improving power efficiency facilitating wireless operation. The custom application-specific integrated circuit (ASIC) combines recording and stimulation channels with a power management unit, allowing the system to be powered by an ultra-light Li-ion battery. Additionally, the µLED drivers include a high-resolution arbitrary waveform generation mode for shaping of µLED current pulses to preemptively reduce artifacts. A prototype IC occupies 7.66 mm2, consumes 3.04 mW under typical operating conditions, and the optical pulse shaping scheme can attenuate stimulation artifacts by up to 3x with a Gaussian-rise pulse rise time under 1 ms.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147674/1/mendrela_1.pd

Real-Time Digital Simulators: A Comprehensive Study on System Overview, Application, and Importance

The multifarious improvements in computational and simulation tools have brought tremendous progress in the field of designing, testing and analyzing technologies. In this paper, the technological aspects and the concept of modern real-time digital simulators are presented. The real-time simulator functions in real time, thus it produces continuous output that realistically represents the conditions of a real system. Also, in a real-time simulator the user can test physical devices. Therefore, it is of great importance to understand the features and roles of the advanced simulator technologies. Also, User-friendly system interface, easy application in system design and testing, and most importantly cost effectiveness are the most desire features for implying these simulator into a research. Therefore, this paper summarizes all significant features by considering the above-mentioned facts of some most popular, globally, and commercially available simulator technologies. Real Time Digital Simulators (RTDS), OPAL-RT, Network Torsion Machine Control (NETOMAC), dSPACE, Real-Time solution by MathWorks (xPC target, Real-Time Windows target), Power_system Online_simulation Unveil Your Analysis (POUYA) Simulator and Typhoon HIL Simulator are discussed in this review paper based on the accessibility of information. A summarization of these simulators’ background, hardware, software and communication protocols are presented. Applications of these above-mentioned simulators are also added to understand the potentials of these simulators

A Comprehensive Study of Dual Active Bridge Converter and Deep Belief Network Controller for Bi-directional Solid State Transformers

Department of Electrical EngineeringThis dissertation presents a comprehensive study of Dual Active Bridge (DAB) converter and Deep Belief Network (DBN) controller for bi-directional Solid State Transformers (SSTs). The first contribution is to propose a dc-dc DAB converter as a single stage SST. The proposed converter topology consists of two active H-bridges and one high-frequency transformer. Output voltage can be regulated when input voltage changes by phase shift modulation. Power is transferred from the first bridge to the second bridge. It analyzes the steady-state operation. The second contribution is to develop an average model for dc-dc DAB converters. The transformer current in DAB converter is purely ac, making continuous-time modeling is difficult. Instead, the proposed approach uses the only 1st order terms of transformer current and capacitor voltage as state variables. The third contribution is the controller design of a dc-dc DAB converter. The PI gains are allowed to vary within a predetermined range and therefore eliminate the problems from the conventional PI controller. The performance of the proposed artificial intelligence gain scheduled PI controller is simulated and compared with the conventional fixed PI controller under steady state error, responding time and load disturbances. The experimental system of DAB converter is implemented using digital signal processing unit, Texas Instrument TMS320F28335 control board, to examine and verify the performance of the proposed controller under various operating conditions. Simulation and experimental results show a good improvement in transient as well as steady state response of the proposed controller. However, power efficiency, computation burden and complexity of algorithm are disadvantage of proposed algorithm.ope

Exploiting All-Programmable System on Chips for Closed-Loop Real-Time Neural Interfaces

High-density microelectrode arrays (HDMEAs) feature thousands of recording electrodes in a single chip with an area of few square millimeters. The obtained electrode density is comparable and even higher than the typical density of neuronal cells in cortical cultures. Commercially available HDMEA-based acquisition systems are able to record the neural activity from the whole array at the same time with submillisecond resolution. These devices are a very promising tool and are increasingly used in neuroscience to tackle fundamental questions regarding the complex dynamics of neural networks. Even if electrical or optical stimulation is generally an available feature of such systems, they lack the capability of creating a closed-loop between the biological neural activity and the artificial system. Stimuli are usually sent in an open-loop manner, thus violating the inherent working basis of neural circuits that in nature are constantly reacting to the external environment. This forbids to unravel the real mechanisms behind the behavior of neural networks. The primary objective of this PhD work is to overcome such limitation by creating a fullyreconfigurable processing system capable of providing real-time feedback to the ongoing neural activity recorded with HDMEA platforms. The potentiality of modern heterogeneous FPGAs has been exploited to realize the system. In particular, the Xilinx Zynq All Programmable System on Chip (APSoC) has been used. The device features reconfigurable logic, specialized hardwired blocks, and a dual-core ARM-based processor; the synergy of these components allows to achieve high elaboration performances while maintaining a high level of flexibility and adaptivity. The developed system has been embedded in an acquisition and stimulation setup featuring the following platforms: \u2022 3\ub7Brain BioCam X, a state-of-the-art HDMEA-based acquisition platform capable of recording in parallel from 4096 electrodes at 18 kHz per electrode. \u2022 PlexStim\u2122 Electrical Stimulator System, able to generate electrical stimuli with custom waveforms to 16 different output channels. \u2022 Texas Instruments DLP\uae LightCrafter\u2122 Evaluation Module, capable of projecting 608x684 pixels images with a refresh rate of 60 Hz; it holds the function of optical stimulation. All the features of the system, such as band-pass filtering and spike detection of all the recorded channels, have been validated by means of ex vivo experiments. Very low-latency has been achieved while processing the whole input data stream in real-time. In the case of electrical stimulation the total latency is below 2 ms; when optical stimuli are needed, instead, the total latency is a little higher, being 21 ms in the worst case. The final setup is ready to be used to infer cellular properties by means of closed-loop experiments. As a proof of this concept, it has been successfully used for the clustering and classification of retinal ganglion cells (RGCs) in mice retina. For this experiment, the light-evoked spikes from thousands of RGCs have been correctly recorded and analyzed in real-time. Around 90% of the total clusters have been classified as ON- or OFF-type cells. In addition to the closed-loop system, a denoising prototype has been developed. The main idea is to exploit oversampling techniques to reduce the thermal noise recorded by HDMEAbased acquisition systems. The prototype is capable of processing in real-time all the input signals from the BioCam X, and it is currently being tested to evaluate the performance in terms of signal-to-noise-ratio improvement

APPROXIMATE COMPUTING BASED PROCESSING OF MEA SIGNALS ON FPGA

The Microelectrode Array (MEA) is a collection of parallel electrodes that may measure the extracellular potential of nearby neurons. It is a crucial tool in neuroscience for researching the structure, operation, and behavior of neural networks. Using sophisticated signal processing techniques and architectural templates, the task of processing and evaluating the data streams obtained from MEAs is a computationally demanding one that needs time and parallel processing.This thesis proposes enhancing the capability of MEA signal processing systems by using approximate computing-based algorithms. These algorithms can be implemented in systems that process parallel MEA channels using the Field Programmable Gate Arrays (FPGAs). In order to develop approximate signal processing algorithms, three different types of approximate adders are investigated in various configurations. The objective is to maximize performance improvements in terms of area, power consumption, and latency associated with real-time processing while accepting lower output accuracy within certain bounds. On FPGAs, the methods are utilized to construct approximate processing systems, which are then contrasted with the precise system. Real biological signals are used to evaluate both precise and approximative systems, and the findings reveal notable improvements, especially in terms of speed and area. Processing speed enhancements reach up to 37.6%, and area enhancements reach 14.3% in some approximate system modes without sacrificing accuracy. Additional cases demonstrate how accuracy, area, and processing speed may be traded off. Using approximate computing algorithms allows for the design of real-time MEA processing systems with higher speeds and more parallel channels. The application of approximate computing algorithms to process biological signals on FPGAs in this thesis is a novel idea that has not been explored before

Wired, wireless and wearable bioinstrumentation for high-precision recording of bioelectrical signals in bidirectional neural interfaces

It is widely accepted by the scientific community that bioelectrical signals, which can be used for the identification of neurophysiological biomarkers indicative of a diseased or pathological state, could direct patient treatment towards more effective therapeutic strategies. However, the design and realisation of an instrument that can precisely record weak bioelectrical signals in the presence of strong interference stemming from a noisy clinical environment is one of the most difficult challenges associated with the strategy of monitoring bioelectrical signals for diagnostic purposes. Moreover, since patients often have to cope with the problem of limited mobility being connected to bulky and mains-powered instruments, there is a growing demand for small-sized, high-performance and ambulatory biopotential acquisition systems in the Intensive Care Unit (ICU) and in High-dependency wards. Furthermore, electrical stimulation of specific target brain regions has been shown to alleviate symptoms of neurological disorders, such as Parkinson’s disease, essential tremor, dystonia, epilepsy etc. In recent years, the traditional practice of continuously stimulating the brain using static stimulation parameters has shifted to the use of disease biomarkers to determine the intensity and timing of stimulation. The main motivation behind closed-loop stimulation is minimization of treatment side effects by providing only the necessary stimulation required within a certain period of time, as determined from a guiding biomarker. Hence, it is clear that high-quality recording of local field potentials (LFPs) or electrocorticographic (ECoG) signals during deep brain stimulation (DBS) is necessary to investigate the instantaneous brain response to stimulation, minimize time delays for closed-loop neurostimulation and maximise the available neural data. To our knowledge, there are no commercial, small, battery-powered, wearable and wireless recording-only instruments that claim the capability of recording ECoG signals, which are of particular importance in closed-loop DBS and epilepsy DBS. In addition, existing recording systems lack the ability to provide artefact-free high-frequency (> 100 Hz) LFP recordings during DBS in real time primarily because of the contamination of the neural signals of interest by the stimulation artefacts. To address the problem of limited mobility often encountered by patients in the clinic and to provide a wide variety of high-precision sensor data to a closed-loop neurostimulation platform, a low-noise (8 nV/√Hz), eight-channel, battery-powered, wearable and wireless multi-instrument (55 × 80 mm2) was designed and developed. The performance of the realised instrument was assessed by conducting both ex vivo and in vivo experiments. The combination of desirable features and capabilities of this instrument, namely its small size (~one business card), its enhanced recording capabilities, its increased processing capabilities, its manufacturability (since it was designed using discrete off-the-shelf components), the wide bandwidth it offers (0.5 – 500 Hz) and the plurality of bioelectrical signals it can precisely record, render it a versatile tool to be utilized in a wide range of applications and environments. Moreover, in order to offer the capability of sensing and stimulating via the same electrode, novel real-time artefact suppression methods that could be used in bidirectional (recording and stimulation) system architectures are proposed and validated. More specifically, a novel, low-noise and versatile analog front-end (AFE), which uses a high-order (8th) analog Chebyshev notch filter to suppress the artefacts originating from the stimulation frequency, is presented. After defining the system requirements for concurrent LFP recording and DBS artefact suppression, the performance of the realised AFE is assessed by conducting both in vitro and in vivo experiments using unipolar and bipolar DBS (monophasic pulses, amplitude ranging from 3 to 6 V peak-to-peak, frequency 140 Hz and pulse width 100 µs). Under both in vitro and in vivo experimental conditions, the proposed AFE provided real-time, low-noise and artefact-free LFP recordings (in the frequency range 0.5 – 250 Hz) during stimulation. Finally, a family of tunable hardware filter designs and a novel method for real-time artefact suppression that enables wide-bandwidth biosignal recordings during stimulation are also presented. This work paves the way for the development of miniaturized research tools for closed-loop neuromodulation that use a wide variety of bioelectrical signals as control signals.Open Acces

Embedded electronic systems driven by run-time reconfigurable hardware

Abstract This doctoral thesis addresses the design of embedded electronic systems based on run-time reconfigurable hardware technology –available through SRAM-based FPGA/SoC devices– aimed at contributing to enhance the life quality of the human beings. This work does research on the conception of the system architecture and the reconfiguration engine that provides to the FPGA the capability of dynamic partial reconfiguration in order to synthesize, by means of hardware/software co-design, a given application partitioned in processing tasks which are multiplexed in time and space, optimizing thus its physical implementation –silicon area, processing time, complexity, flexibility, functional density, cost and power consumption– in comparison with other alternatives based on static hardware (MCU, DSP, GPU, ASSP, ASIC, etc.). The design flow of such technology is evaluated through the prototyping of several engineering applications (control systems, mathematical coprocessors, complex image processors, etc.), showing a high enough level of maturity for its exploitation in the industry.Resumen Esta tesis doctoral abarca el diseño de sistemas electrónicos embebidos basados en tecnología hardware dinámicamente reconfigurable –disponible a través de dispositivos lógicos programables SRAM FPGA/SoC– que contribuyan a la mejora de la calidad de vida de la sociedad. Se investiga la arquitectura del sistema y del motor de reconfiguración que proporcione a la FPGA la capacidad de reconfiguración dinámica parcial de sus recursos programables, con objeto de sintetizar, mediante codiseño hardware/software, una determinada aplicación particionada en tareas multiplexadas en tiempo y en espacio, optimizando así su implementación física –área de silicio, tiempo de procesado, complejidad, flexibilidad, densidad funcional, coste y potencia disipada– comparada con otras alternativas basadas en hardware estático (MCU, DSP, GPU, ASSP, ASIC, etc.). Se evalúa el flujo de diseño de dicha tecnología a través del prototipado de varias aplicaciones de ingeniería (sistemas de control, coprocesadores aritméticos, procesadores de imagen, etc.), evidenciando un nivel de madurez viable ya para su explotación en la industria.Resum Aquesta tesi doctoral està orientada al disseny de sistemes electrònics empotrats basats en tecnologia hardware dinàmicament reconfigurable –disponible mitjançant dispositius lògics programables SRAM FPGA/SoC– que contribueixin a la millora de la qualitat de vida de la societat. S’investiga l’arquitectura del sistema i del motor de reconfiguració que proporcioni a la FPGA la capacitat de reconfiguració dinàmica parcial dels seus recursos programables, amb l’objectiu de sintetitzar, mitjançant codisseny hardware/software, una determinada aplicació particionada en tasques multiplexades en temps i en espai, optimizant així la seva implementació física –àrea de silici, temps de processat, complexitat, flexibilitat, densitat funcional, cost i potència dissipada– comparada amb altres alternatives basades en hardware estàtic (MCU, DSP, GPU, ASSP, ASIC, etc.). S’evalúa el fluxe de disseny d’aquesta tecnologia a través del prototipat de varies aplicacions d’enginyeria (sistemes de control, coprocessadors aritmètics, processadors d’imatge, etc.), demostrant un nivell de maduresa viable ja per a la seva explotació a la indústria

A Closed-Loop Deep Brain Stimulation Device With a Logarithmic Pipeline ADC.

This dissertation is a summary of the research on integrated closed-loop deep brain stimulation for treatment of Parkinson’s disease. Parkinson's disease is a progressive disorder of the central nervous system affecting more than three million people in the United States. Deep Brain Stimulation (DBS) is one of the most effective treatments of Parkinson’s symptoms. DBS excites the Subthalamic Nucleus (STN) with a high frequency electrical signal. The proposed device is a single-chip closed-loop DBS (CDBS) system. Closed-loop feedback of sensed neural activity promises better control and optimization of stimulation parameters than with open-loop devices. Thanks to a novel architecture, the prototype system incorporates more functionality yet consumes less power and area compared to other systems. Eight front-end low-noise neural amplifiers (LNAs) are multiplexed to a single high-dynamic-range logarithmic, pipeline analog-to-digital converter (ADC). To save area and power consumption, a high dynamic-range log ADC is used, making analog automatic gain control unnecessary. The redundant 1.5b architecture relaxes the requirements for the comparator accuracy and comparator reference voltage accuracy. Instead of an analog filter, an on-chip digital filter separates the low frequency neural field potential signal from the neural spike energy. An on-chip controller generates stimulation patterns to control the 64 on-chip current-steering DACs. The 64 DACs are formed as a cascade of a single shared 2-bit coarse current DAC and 64 individual bi-directional 4-bit fine DACs. The coarse/fine configuration saves die area since the MSB devices tend to be large. Real-time neural activity was recorded with the prototype device connected to microprobes that were chronically implanted in two Long Evans rats. The recorded in-vivo signal clearly shows neural spikes of 10.2 dB signal-to-noise ratio (SNR) as well as a periodic artifact from neural stimulation. The recorded neural information has been analyzed with single unit sorting and principal component analysis (PCA). The PCA scattering plots from multi-layers of cortex represent diverse information from either single or multiple neural sources. The single-unit neural sorting analysis along with PCA verifies the feasibility of the implantable CDBS device for to in-vivo neural recording interface applications.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/60733/1/milaca_1.pd