High Performance Local Oscillator Design for Next Generation Wireless Communication

Local Oscillator (LO) is an essential building block in modern wireless radios. In modern wireless radios, LO often serves as a reference of the carrier signal to modulate or demod- ulate the outgoing or incoming data. The LO signal should be a clean and stable source, such that the frequency or timing information of the carrier reference can be well-defined. However, as radio architecture evolves, the importance of LO path design has become much more important than before. Of late, many radio architecture innovations have exploited sophisticated LO generation schemes to meet the ever-increasing demands of wireless radio performances. The focus of this thesis is to address challenges in the LO path design for next-generation high performance wireless radios. These challenges include (1) Congested spectrum at low radio frequency (RF) below 5GHz (2) Continuing miniaturization of integrated wireless radio, and (3) Fiber-fast (>10Gb/s) mm-wave wireless communication. The thesis begins with a brief introduction of the aforementioned challenges followed by a discussion of the opportunities projected to overcome these challenges. To address the challenge of congested spectrum at frequency below 5GHz, novel ra- dio architectures such as cognitive radio, software-defined radio, and full-duplex radio have drawn significant research interest. Cognitive radio is a radio architecture that opportunisti- cally utilize the unused spectrum in an environment to maximize spectrum usage efficiency. Energy-efficient spectrum sensing is the key to implementing cognitive radio. To enable energy-efficient spectrum sensing, a fast-hopping frequency synthesizer is an essential build- ing block to swiftly sweep the carrier frequency of the radio across the available spectrum. Chapter 2 of this thesis further highlights the challenges and trade-offs of the current LO gen- eration scheme for possible use in sweeping LO-based spectrum analysis. It follows by intro- duction of the proposed fast-hopping LO architecture, its implementation and measurement results of the validated prototype. Chapter 3 proposes an embedded phase-shifting LO-path design for wideband RF self-interference cancellation for full-duplex radio. It demonstrates a synergistic design between the LO path and signal to perform self-interference cancellation. To address the challenge of continuing miniaturization of integrated wireless radio, ring oscillator-based frequency synthesizer is an attractive candidate due to its compactness. Chapter 4 discussed the difficulty associated with implementing a Phase-Locked Loop (PLL) with ultra-small form-factor. It further proposes the concept sub-sampling PLL with time- based loop filter to address these challenges. A 65nm CMOS prototype and its measurement result are presented for validation of the concept. In shifting from RF to mm-wave frequencies, the performance of wireless communication links is boosted by significant bandwidth and data-rate expansion. However, the demand for data-rate improvement is out-pacing the innovation of radio architectures. A >10Gb/s mm-wave wireless communication at 60GHz is required by emerging applications such as virtual-reality (VR) headsets, inter-rack data transmission at data center, and Ultra-High- Definition (UHD) TV home entertainment systems. Channel-bonding is considered to be a promising technique for achieving >10Gb/s wireless communication at 60GHz. Chapter 5 discusses the fundamental radio implementation challenges associated with channel-bonding for 60GHz wireless communication and the pros and cons of prior arts that attempted to address these challenges. It is followed by a discussion of the proposed 60GHz channel- bonding receiver, which utilizes only a single PLL and enables both contiguous and non- contiguous channel-bonding schemes. Finally, Chapter 6 presents the conclusion of this thesis

Rapid-scan electron paramagnetic resonance using an EPR-on-a-Chip sensor

Electron paramagnetic resonance (EPR) spectroscopy is the method of choice to investigate and quantify paramagnetic species in many scientific fields, including materials science and the life sciences. Common EPR spectrometers use electromagnets and microwave (MW) resonators, limiting their application to dedicated lab environments. Here, we present an improved design of a miniaturized EPR spectrometer implemented on a silicon microchip (EPR-on-a-chip, EPRoC). In place of a microwave resonator, EPRoC uses an array of injection-locked voltage-controlled oscillators (VCOs), each incorporating a 200 μm diameter coil, as a combined microwave source and detector. The individual miniaturized VCO elements provide an excellent spin sensitivity reported to be about 4 × 109spins/√Hz, which is extended by the array over a larger area for improved concentration sensitivity. A striking advantage of this design is the possibility to sweep the MW frequency instead of the magnetic field, which allows the use of smaller, permanent magnets instead of the bulky and powerhungry electromagnets required for field-swept EPR. Here, we report rapid scan EPR (RS-EPRoC) experiments performed by sweeping the frequency of the EPRoC VCO array. RS-EPRoC spectra demonstrate an improved SNR by approximately two orders of magnitude for similar signal acquisition times compared to continuous wave (CW-EPRoC) methods, which may improve the absolute spin and concentration sensitivity of EPR-on-a-Chip at 14 GHz to about 6 × 107 spins/√Hz and 3.6 nM⁄√Hz, respectively

SILICON TERAHERTZ ELECTRONICS: CIRCUITS AND SYSTEMS FOR FUTURE APPLICATIONS

The terahertz frequency bands are gaining increasing attention these days for the potential applications in imaging, sensing, spectroscopy, and communication. These applications can be used in a wide range of fields, such as military, security, biomedical analysis, material science, astronomy, etc. Unfortunately, utilizing these frequency bands is very challenging due to the notorious ”terahertz gap”. Consequently, current terahertz systems are very bulky and expensive, sometimes even require cryogenic conditions. Silicon terahertz electronics now becomes very attractive, since it can achieve significantly lower cost and make portable consumer terahertz devices feasible. However, due to the limited device fmax and low breakdown voltage, signal generation and processing on silicon platform in this frequency range is challenging. This thesis aims to tackle these challenges and implement high-performance terahertz systems. First of all, the devices are investigated under the terahertz frequency range and optimum termination conditions for maximizing the efficacy of the devices is derived. Then, novel passive surrounding networks are designed to provide the devices with the optimal termination conditions to push the performances of the terahertz circuit blocks. Finally, the high-performance circuit blocks are used to build terahertz systems, and system-level innovations are also proposed to push the state of the art forward. In Chapter 2, using a device-centric bottom-up design method, a 210-GHz harmonic oscillator is designed. With the parasitic tuning mechanism, a wide frequency tuning range is achieved without using lossy varactors. A passive network based on the return-path gap coupler and self-feeding structure is also designed to provide optimal terminations for the active devices to maximize the harmonic power generation. Fabricated with a 0.13-um SiGe BiCMOS process, the oscillator is highly compact with a core size of only 290x95 um2. The output frequency can be tuned from 197.5 GHz to 219.7 GHz, which is around 10.6% compared to the center frequency. It also achieves a peak output power and dc-to-RF efficiency of 1.4 dBm and 2.4%, respectively. The measured output phase noise at 1 MHz offset is -87.5 dBc/Hz. The high power, wide tuning range, low phase noise, as well as compact size, make this oscillator very suitable for terahertz systems integration. In Chapter 3, the design of a 320-GHz fully-integrated terahertz imaging system is described. The system is composed of a phase-locked high-power transmitter and a coherent high-sensitivity subharmonic-mixing receiver, which are fabricated using a 0.13-um SiGe BiCMOS technology. To enhance the imaging sensitivity, a heterodyne coherent detection scheme is utilized. To obtain frequency coherency, fully-integrated phase-locked loops are implemented on both the transmitter and receiver chips. According to the measurement, consuming a total dc power of 605 mW, the transmitter chip achieves a peak radiated power of 2 mW and a peak EIRP of 21.1 dBm. The receiver chip achieves an equivalent incoherent responsivity of more than 7.26 MV/W and a sensitivity of 70.1 pW under an integration bandwidth of 1 kHz, with a total dc power consumption of 117 mW. The achieved sensitivity with this proposed coherent imaging transceiver is around ten times better compared with other state-of-the-art incoherent imagers. In Chapter 4, a spatial-orthogonal ASK transmitter architecture for high-speed terahertz wireless communication is presented. The self-sustaining oscillator-based transmitter architecture has an ultra-compact size and excellent power efficiency. With the proposed high-speed constant-load switch, significantly reduced modulation loss is achieved. Using polarization diversity and multi-level modulation, the throughput is largely enhanced. Array configuration is also adopted to enhance the link budget for higher signal quality and longer communication range. Fabricated in a 0.13-um SiGe BiCMOS technology, the 220-GHz transmitter prototype achieves an EIRP of 21 dBm and dc-to- THz-radiation efficiency of 0.7% in each spatial channel. A 24.4-Gb/s total data rate over a 10-cm communication range is demonstrated. With an external Teflon lens system, the demonstrated communication range is further extended to 52 cm. Compared with prior art, this prototype demonstrates much higher transmitter efficiency. In Chapter 5, an entirely-on-chip frequency-stabilization feedback mechanism is proposed, which avoids the use of both frequency dividers and off-chip references, achieving much lower system integration cost and power consumption. Using this mechanism, a 301.7-to-331.8-GHz source prototype is designed in a 0.13-um SiGe BiCMOS technology. According to the measurement, the source consumes a dc power of only 51.7 mW. The output phase noise is -71.1 and -75.2 dBc/Hz at 100 kHz and 1 MHz offset, respectively. A -13.9-dBm probed output power is also achieved. Overall, the prototype source demonstrates the largest output frequency range and lowest power consumption while achieving comparable phase noise and output power performances with respect to the state of the art. All the designs demonstrated in this thesis achieve good performances and push the state of the art forward, paving the way for implementation of more sophisticated terahertz circuits and systems for future applications

Low Power Analog Processing for Ultra-High-Speed Receivers with RF Correlation

Ultra-high-speed data communication receivers (Rxs) conventionally require analog digital converters (ADC)s with high sampling rates which have design challenges in terms of adequate resolution and power. This leads to ultra-high-speed Rxs utilising expensive and bulky high-speed oscilloscopes which are extremely inefficient for demodulation, in terms of power and size. Designing energy-efficient mixed-signal and baseband units for ultra-high-speed Rxs requires a paradigm approach detailed in this paper that circumvents the use of power-hungry ADCs by employing low-power analog processing. The low-power analog Rx employs direct-demodulation with RF correlation using low-power comparators. The Rx is able to support multiple modulations with highest modulation of 16-QAM reported so far for direct-demodulation with RF correlation. Simulations using Matlab, Simulink R2020a® indicate sufficient symbol-error rate (SER) performance at a symbol rate of 8 GS/s for the 71 GHz Urban Micro Cell and 140 GHz indoor channels. Power analysis undertaken with current analog, hybrid and digital beamforming approaches requiring ADCs indicates considerable power savings. This novel approach can be adopted for ultra-high-speed Rxs envisaged for beyond fifth generation (B5G)/sixth generation (6G)/ terahertz (THz) communication without the power-hungry ADCs, leading to low-power integrated design solutions

Integrated photonics for millimetre wave transmitters and receivers

This PhD thesis entitled “Integrated photonics for millimetre wave transmitters and receivers” aimed at investigating the possibility of employing the uni-traveling carrier photodiode (UTC-PD) in millimetre wave (MMW) wireless receivers and, eventually, demonstrating a photonic integrated transceiver, by exploiting the concept of optically-pumped mixing (OPM). Previously, the UTC-PD has been successfully demonstrated as an OPM, by mixing an optically-generated local oscillator (LO) with a high frequency RF signal to generate a replica of the RF signal at a low intermediate frequency (IF), defined by the difference between the LO and the RF signal. This concept forms the foundation of this PhD thesis. The principal idea is to deploy the UTC-PD mixer in MMW wireless receivers to down-convert the high frequency data signal into a low frequency IF, where it can be easily processed and recovered. The main challenge to this approach is the low conversion efficiency of the UTC-PD mixer. For example, a conversion loss of 32 dB has been reported at 100 GHz. Also, the detection bandwidth in previous demonstrations was very narrow (around 100 Hz), which is too narrow to be useful in high-speed data communications. Consequently, a significant effort was made, in this thesis, to improve these parameters before the implementation in wireless receivers. The characterization and optimization works done in this thesis on the input parameters to the UTC-PD mixer have advanced the state of the art significantly. For example, conversion losses as low as 22 dB have been reported here. Also, the detection bandwidth has been increased to up to 10 GHz, allowing for multi-Gbps communication links. Based on these promising results, proof of concept wireless data transmission experiments were successfully conducted at different carrier frequencies (33 GHz, 35 GHz, and 60 GHz) using separate non-integrated UTC-PDs at the receiver with speeds of up to 5 Gbps. To the best of the author’s knowledge, this is the first demonstration of the UTC-PD at the receiver. Upon these successful demonstrations, further research was done on a photonic integrated circuit, which comprises UTC-PDs, lasers, optical amplifiers and modulators. The outcome of this research was the first demonstration of a photonic integrated transceiver. This transceiver is suitable for short distance communications and could find interesting applications in 5G and future networks, including: high definition (HD) video streaming, file transfer, and wireless backhaul

Calibrated Continuous-Time Sigma-Delta Modulators

To provide more information mobility, many wireless communication systems such as WCDMA and EDGE in phone systems, bluetooth and WIMAX in communication networks have been recently developed. Recent efforts have been made to build the allin- one next generation device which integrates a large number of wireless services into a single receiving path in order to raise the competitiveness of the device. Among all the receiver architectures, the high-IF receiver presents several unique properties for the next generation receiver by digitalizing the signal at the intermediate frequency around a few hundred MHz. In this architecture, the modulation/demodulation schemes, protocols, equalization, etc., are all determined in a software platform that runs in the digital signal processor (DSP) or FPGA. The specifications for most of front-end building blocks are relaxed, except the analog-to-digital converter (ADC). The requirements of large bandwidth, high operational frequency and high resolution make the design of the ADC very challenging. Solving the bottleneck associated with the high-IF receiver architecture is a major focus of many ongoing research efforts. In this work, a 6th-order bandpass continuous time sigma-delta ADC with measured 68.4dB SNDR at 10MHz bandwidth to accommodate video applications is proposed. Tuned at 200 MHz, the fs/4 architecture employs an 800 MHz clock frequency. By making use of a unique software-based calibration scheme together with the tuning properties of the bandpass filters developed under the umbrella of this project, the ADC performance is optimized automatically to fulfill all requirements for the high-IF architecture. In a separate project, other critical design issues for continuous-time sigma-delta ADCs are addressed, especially the issues related to unit current source mismatches in multi-level DACs as well as excess loop delays that may cause loop instability. The reported solutions are revisited to find more efficient architectures. The aforementioned techniques are used for the design of a 25MHz bandwidth lowpass continuous-time sigma-delta modulator with time-domain two-step 3-bit quantizer and DAC for WiMAX applications. The prototype is designed by employing a level-to-pulse-width modulation (PWM) converter followed by a single-level DAC in the feedback path to translate the typical digital codes into PWM signals with the proposed pulse arrangement. Therefore, the non-linearity issue from current source mismatch in multi-level DACs is prevented. The jitter behavior and timing mismatch issue of the proposed time-based methods are fully analyzed. The measurement results of a chip prototype achieving 67.7dB peak SNDR and 78dB SFDR in 25MHz bandwidth properly demonstrate the design concepts and effectiveness of time-based quantization and feedback. Both continuous-time sigma-delta ADCs were fabricated in mainstream CMOS 0.18um technologies, which are the most popular in today?s consumer electronics industry

Development of a Waveform Sampling ASIC with Femtosecond Timing for a Low Occupancy Vertex Detector.

Ph.D. Thesis. University of Hawaiʻi at Mānoa 2018

Next generation RFID telemetry design for biomedical implants.

The design and development of a Radio Frequency Identification (RFID) based pressure-sensing system to increase the range of current Intra-Ocular Pressure (IOP) sensing systems is described in this dissertation. A large number of current systems use near-field inductive coupling for the transfer of energy and data, which limits the operational range to only a few centimeters and does not allow for continuous monitoring of pressure. Increasing the powering range of the telemetry system will offer the possibility of continuous monitoring since the reader can be attached to a waist belt or put on a night stand when sleeping. The system developed as part of this research operates at Ultra-High Frequencies (UHF) and makes use of the electromagnetic far field to transfer energy and data, which increases the potential range of operation and allows for the use of smaller antennas. The system uses a novel electrically small antenna (ESA) to receive the incident RF signal. A four stage Schottky circuit rectifies and multiplies the received RF signal and provides DC power to a Colpitts oscillator. The oscillator is connected to a pressure sensor and provides an output signal frequency that is proportional to the change in pressure. The system was fabricated using a mature, inexpensive process. The performance of the system compares well with current state of the art, but uses a smaller antenna and a less expensive fabrication process. The system was able to operate over the desired range of 1 m using a half-wave dipole antenna. It was possible to power the system over a range of at least 6.4 cm when the electrically small antenna was used as the receiving antenna

Ultra-Low-Power Sensors and Receivers for IoT Applications

The combination of ultra-low power analog front-ends and CMOS-compatible transducers enable new applications, such as environmental monitors, household appliances, health trackers, etc. that are seamlessly integrated into our daily lives. Furthermore, wireless connectivity allows many of these sensors to operate both independently and collectively. These techniques collectively fulfil the recent surge of internet-of-things (IoT) applications that have the potential to fundamentally change daily life for millions of people.In this dissertation, the circuit and system design of wireless receivers and sensors is presented that explores the challenges of implementing long lifespan, high accuracy, and large coverage range IoT sensor networks. The first is a wake-up receiver (WuRX), which continuously monitors the RF environment to wake up a higher-power radio upon detection of a predetermined RF signature. This work both improves sensitivity and reduces power over prior art through a multi-faceted design featuring an impedance transformation network with large passive voltage gain, an active envelope detector with high input impedance to facilitate large passive voltage gain, a low-power precision comparator, and a low-leakage digital baseband correlator.Although pushing the prior WuRX performance boundary by orders of magnitude, the first work shows moderate sensitivity, inferior temperature robustness, and large area with external lumped components. Thus, the second work shows a miniaturized WuRX that is temperature-compensated, yet still consumes only nano-watt power and millimeter area while operating at 9 GHz. To further reduce the area, a global common-mode feedback is utilized across the envelope detector and baseband amplifier that eliminates the need for off-chip ac-coupling components. Multiple temperature-compensation techniques are proposed to maintain constant bandwidth of the signal path and constant clock frequency. Both WuRXs operate at 0.4 V supply, consume near-zero power and achieve ~-70 dBm sensitivity.Lastly, the first reported CMOS 2-in-1 relative humidity and temperature sensor is presented. A unified analog front-end interfaces on-chip transducers and converts the inputs into a frequency vis a high-linearity frequency-locked loop. An incomplete-settling switched-capacitor-based Wheatstone bridge is proposed to sense the inputs in a power-efficient fashion