1 research outputs found
ULTRA-LOW-JITTER, MMW-BAND FREQUENCY SYNTHESIZERS BASED ON A CASCADED ARCHITECTURE
Department of Electrical EngineeringThis thesis presents an ultra-low-jitter, mmW-band frequency synthesizers based on a cascaded
architecture. First, the mmW-band frequency synthesizer based on a CP PLL is presented. At the
first stage, the CP PLL operating at GHz-band frequencies generated low-jitter output signals due
to a high-Q VCO. At the second stage, an ILFM operating at mmW-band frequencies has a wide
injection bandwidth, so that the jitter performance of the mmW-band output signals is determined
by the GHz-range PLL. The proposed ultra-low-jitter, mmW-band frequency synthesizer based on
a CP PLL, fabricated in a 65-nm CMOS technology, generated output signals from GHz-band
frequencies to mmW-band frequencies, achieving an RMS jitter of 206 fs and an IPN of ???31 dBc.
The active silicon area and the total power consumption were 0.32 mm2 and 42 mW, respectively.
However, due to a large in-band phase noise contribution of a PFD and a CP in the CP PLL, this
first stage was difficult to achieve an ultra-low in-band phase noise. Second, to improve the in-band
phase noise further, the mmW-band frequency synthesizer based on a digital SSPLL is presented.
At the first stage, the digital SSPLL operating at GHz-band frequencies generated ultra-low-jitter
output signals due to its sub-sampling operation and a high-Q GHz VCO. To minimize the
quantization noise of the voltage quantizer in the digital SSPLL, this thesis presents an OSVC as a
voltage quantizer while a small amount of power was consumed. The proposed ultra-low-jitter,
mmW-band frequency synthesizer fabricated in a 65-nm CMOS technology, generated output
signals from GHz-band frequencies to mmW-band frequencies, achieving an RMS jitter of 77 fs
and an IPN of ???40 dBc. The active silicon area and the total power consumption were 0.32 mm2 and
42 mW, respectively.clos