Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Thermal-Aware Networked Many-Core Systems

Advancements in IC processing technology has led to the innovation and growth happening in the consumer electronics sector and the evolution of the IT infrastructure supporting this exponential growth. One of the most difficult obstacles to this growth is the removal of large amount of heatgenerated by the processing and communicating nodes on the system. The scaling down of technology and the increase in power density is posing a direct and consequential effect on the rise in temperature. This has resulted in the increase in cooling budgets, and affects both the life-time reliability and performance of the system. Hence, reducing on-chip temperatures has become a major design concern for modern microprocessors. This dissertation addresses the thermal challenges at different levels for both 2D planer and 3D stacked systems. It proposes a self-timed thermal monitoring strategy based on the liberal use of on-chip thermal sensors. This makes use of noise variation tolerant and leakage current based thermal sensing for monitoring purposes. In order to study thermal management issues from early design stages, accurate thermal modeling and analysis at design time is essential. In this regard, spatial temperature profile of the global Cu nanowire for on-chip interconnects has been analyzed. It presents a 3D thermal model of a multicore system in order to investigate the effects of hotspots and the placement of silicon die layers, on the thermal performance of a modern ip-chip package. For a 3D stacked system, the primary design goal is to maximise the performance within the given power and thermal envelopes. Hence, a thermally efficient routing strategy for 3D NoC-Bus hybrid architectures has been proposed to mitigate on-chip temperatures by herding most of the switching activity to the die which is closer to heat sink. Finally, an exploration of various thermal-aware placement approaches for both the 2D and 3D stacked systems has been presented. Various thermal models have been developed and thermal control metrics have been extracted. An efficient thermal-aware application mapping algorithm for a 2D NoC has been presented. It has been shown that the proposed mapping algorithm reduces the effective area reeling under high temperatures when compared to the state of the art.Siirretty Doriast

Computational and instrumental developments in quantitative Auger electron analysis.

The technique of quantitative Auger electron spectroscopy (AES) is central to modem surface analysis. Development, both in terms of new instrumental apparatus and the theoretical basis of Auger analysis, has been the subject of intense research. The work presented here investigates two of the current issues surrounding Auger electron spectroscopy and microscopy. The modelling of electron-solid interaction is reviewed, and investigations are carried out into the two well established computational techniques, transport theory and Monte Carlo simulation. The transport mean free path, V and the inelastic mean free path, A* describe electron transport in solids to the first order. Variations in these parameters with energy and atomic number are explored with a view to identifying trends and establishing the extent to which generalisations are valid. Although transport theory calculations have been shown to give an accurate representation of true electron behaviour, their application is largely limited to homogeneous materials. Monte Carlo modeling provides us with a more rigorous treatment of complex experimental conditions. A new Monte Carlo model is presented which allows extension of existing simulations to incorporate heterogeneous multilayered samples. The design of integrated circuits is an extremely fast moving technology, with routine manufacture of nanometric feature sizes now becoming a reality. The second part of this work is devoted to the design of an angle resolved electron spectrometer with a very high resolution field emission electron probe. It is intended that high resolution analysis, coupled with the ability to resolve the azimuthal component of electron trajectories, will offer new insight into the surface features of ultra large scale integrated circuits

Statistical circuit simulations - from ‘atomistic’ compact models to statistical standard cell characterisation

This thesis describes the development and application of statistical circuit simulation methodologies to analyse digital circuits subject to intrinsic parameter fluctuations. The specific nature of intrinsic parameter fluctuations are discussed, and we explain the crucial importance to the semiconductor industry of developing design tools which accurately account for their effects. Current work in the area is reviewed, and three important factors are made clear: any statistical circuit simulation methodology must be based on physically correct, predictive models of device variability; the statistical compact models describing device operation must be characterised for accurate transient analysis of circuits; analysis must be carried out on realistic circuit components. Improving on previous efforts in the field, we posit a statistical circuit simulation methodology which accounts for all three of these factors. The established 3-D Glasgow atomistic simulator is employed to predict electrical characteristics for devices aimed at digital circuit applications, with gate lengths from 35 nm to 13 nm. Using these electrical characteristics, extraction of BSIM4 compact models is carried out and their accuracy in performing transient analysis using SPICE is validated against well characterised mixed-mode TCAD simulation results for 35 nm devices. Static d.c. simulations are performed to test the methodology, and a useful analytic model to predict hard logic fault limitations on CMOS supply voltage scaling is derived as part of this work. Using our toolset, the effect of statistical variability introduced by random discrete dopants on the dynamic behaviour of inverters is studied in detail. As devices scaled, dynamic noise margin variation of an inverter is increased and higher output load or input slew rate improves the noise margins and its variation. Intrinsic delay variation based on CV/I delay metric is also compared using ION and IEFF definitions where the best estimate is obtained when considering ION and input transition time variations. Critical delay distribution of a path is also investigated where it is shown non-Gaussian. Finally, the impact of the cell input slew rate definition on the accuracy of the inverter cell timing characterisation in NLDM format is investigated

Optoelectronics – Devices and Applications

Optoelectronics - Devices and Applications is the second part of an edited anthology on the multifaced areas of optoelectronics by a selected group of authors including promising novices to experts in the field. Photonics and optoelectronics are making an impact multiple times as the semiconductor revolution made on the quality of our life. In telecommunication, entertainment devices, computational techniques, clean energy harvesting, medical instrumentation, materials and device characterization and scores of other areas of R&D the science of optics and electronics get coupled by fine technology advances to make incredibly large strides. The technology of light has advanced to a stage where disciplines sans boundaries are finding it indispensable. New design concepts are fast emerging and being tested and applications developed in an unimaginable pace and speed. The wide spectrum of topics related to optoelectronics and photonics presented here is sure to make this collection of essays extremely useful to students and other stake holders in the field such as researchers and device designers

EUROSENSORS XVII : book of abstracts

Fundação Calouste Gulbenkien (FCG).Fundação para a Ciência e a Tecnologia (FCT)

Technology 2003: The Fourth National Technology Transfer Conference and Exposition, volume 2

Proceedings from symposia of the Technology 2003 Conference and Exposition, Dec. 7-9, 1993, Anaheim, CA, are presented. Volume 2 features papers on artificial intelligence, CAD&E, computer hardware, computer software, information management, photonics, robotics, test and measurement, video and imaging, and virtual reality/simulation