Efficient and Linear CMOS Power Amplifier and Front-end Design for Broadband Fully-Integrated 28-GHz 5G Phased Arrays

Demand for data traffic on mobile networks is growing exponentially with time and on a global scale. The emerging fifth-generation (5G) wireless standard is being developed with millimeter-wave (mm-Wave) links as a key technological enabler to address this growth by a 2020 time frame. The wireless industry is currently racing to deploy mm-Wave mobile services, especially in the 28-GHz band. Previous widely-held perceptions of fundamental propagation limitations were overcome using phased arrays. Equally important for success of 5G is the development of low-power, broadband user equipment (UE) radios in commercial-grade technologies. This dissertation demonstrates design methodologies and circuit techniques to tackle the critical challenge of key phased array front-end circuits in low-cost complementary metal oxide semiconductor (CMOS) technology. Two power amplifier (PA) proof-of-concept prototypes are implemented in deeply scaled 28- nm and 40-nm CMOS processes, demonstrating state-of-the-art linearity and efficiency for extremely broadband communication signals. Subsequently, the 40 nm PA design is successfully embedded into a low-power fully-integrated transmit-receive front-end module. The 28 nm PA prototype in this dissertation is the first reported linear, bulk CMOS PA targeting low-power 5G mobile UE integrated phased array transceivers. An optimization methodology is presented to maximizing power added efficiency (PAE) in the PA output stage at a desired error vector magnitude (EVM) and range to address challenging 5G uplink requirements. Then, a source degeneration inductor in the optimized output stage is shown to further enable its embedding into a two-stage transformer-coupled PA. The inductor helps by broadening inter-stage impedance matching bandwidth, and helping to reduce distortion. Designed and fabricated in 1P7M 28 nm bulk CMOS and using a 1 V supply, the PA achieves +4.2 dBm/9% measured Pout/PAE at −25 dBc EVM for a 250 MHz-wide, 64-QAM orthogonal frequency division multiplexing (OFDM) signal with 9.6 dB peak-to-average power ratio (PAPR). The PA also achieves 35.5%/10% PAE for continuous wave signals at saturation/9.6dB back-off from saturation. To the best of the author’s knowledge, these are the highest measured PAE values among published K- and K a-band CMOS PAs to date. To drastically extend the communication bandwidth in 28 GHz-band UE devices, and to explore the potential of CMOS technology for more demanding access point (AP) devices, the second PA is demonstrated in a 40 nm process. This design supports a signal radio frequency bandwidth (RFBW) >3× the state-of-the-art without degrading output power (i.e. range), PAE (i.e. battery life), or EVM (i.e. amplifier fidelity). The three-stage PA uses higher-order, dual-resonance transformer matching networks with bandwidths optimized for wideband linearity. Digital gain control of 9 dB range is integrated for phased array operation. The gain control is a needed functionality, but it is largely absent from reported high-performance mm-Wave PAs in the literature. The PA is fabricated in a 1P6M 40 nm CMOS LP technology with 1.1 V supply, and achieves Pout/PAE of +6.7 dBm/11% for an 8×100 MHz carrier aggregation 64-QAM OFDM signal with 9.7 dB PAPR. This PA therefore is the first to demonstrate the viability of CMOS technology to address even the very challenging 5G AP/downlink signal bandwidth requirement. Finally, leveraging the developed PA design methodologies and circuits, a low power transmit-receive phased array front-end module is fully integrated in 40 nm technology. In transmit-mode, the front-end maintains the excellent performance of the 40 nm PA: achieving +5.5 dBm/9% for the same 8×100 MHz carrier aggregation signal above. In receive-mode, a 5.5 dB noise figure (NF) and a minimum third-order input intercept point (IIP₃) of −13 dBm are achieved. The performance of the implemented CMOS frontend is comparable to state-of-the-art publications and commercial products that were very recently developed in silicon germanium (SiGe) technologies for 5G communication

KEY FRONT-END CIRCUITS IN MILLIMETER-WAVE SILICON-BASED WIRELESS TRANSMITTERS FOR PHASED-ARRAY APPLICATIONS

Millimeter-wave (mm-Wave) phased arrays have been widely used in numerous wireless systems to perform beam forming and spatial filtering that can enhance the equivalent isotropically radiated power (EIRP) for the transmitter (TX). Regarding the existing phased-array architectures, an mm-Wave transmitter includes several building blocks to perform the desired delivered power and phases for wireless communication. Power amplifier (PA) is the most important building block. It needs to offer several advantages, e.g., high efficiency, broadband operation and high linearity. With the recent escalation of interest in 5G wireless communication technologies, mm-Wave transceivers at the 5G frequency bands (e.g., 28 GHz, 37 GHz, 39 GHz, and 60 GHz) have become an important topic in both academia and industry. Thus, PA design is a critical obstacle due to the challenges associated with implementing wideband, highly efficient and highly linear PAs at mm-Wave frequencies. In this dissertation, we present several PA design innovations to address the aforementioned challenges. Additionally, phase shifter (PS) also plays a key role in a phased-array system, since it governs the beam forming quality and steering capabilities. A high-performance phase shifter should achieve a low insertion loss, a wide phase shifting range, dense phase shift angles, and good input/output matching.Ph.D

A 39GHz Balanced Power Amplifier with Enhanced Linearity in 45 nm SOI CMOS

With the high data rate communication systems that come with fifth-generation (5G) mobile networks, the shift of operation to millimeter-wave frequency becomes inevitable. The expected data rate in 5G is significantly improved over 4G by utilizing the large available channel bandwidth at millimeter wave frequencies and complex data modulation schemes. With this increase in operation frequency, many new challenges arise and research efforts are made to tackle them. Among them, the phased array system is one of the hottest topics as it can be made use of to improve the link budget and overcome the path loss challenge at these frequencies. As the last circuit component in the transmitter's front-end right before the antenna, the power amplifier (PA) is one of the most crucial components with significant effects on overall system performance. Many of the traditional challenges of CMOS PA design such as output power and efficiency, are now compounded with the additional challenges that are imposed on complementary metal-oxide semiconductor (CMOS) PAs in millimeter wave phased array systems. This thesis presents a balanced power amplifier design with enhanced linearity in GlobalFoundries' 45nm silicon-on-insulator (SOI) CMOS technology. By using the balanced topology with each stage terminating with a differential 2-stacked architecture, the PA achieves saturated output power of over 21 dBm. Each of the two identical sub-PAs in the balanced topology uses 2-stage topology with driver and PA co-design method. The linearity is enhanced through careful choice of biasing point and a strategic inter-stage matching network design methodology, resulting in amplitude-to-phase distortion below 1 degree up to the output 1dB compression level of over 19 dBm. The balanced amplifier topology significantly reduces the PA performance variation over mismatched load impedance at the output, thus improving the PA performance over different antenna active impedance caused by varying phased array beam-steering angles. In addition to this, the balanced topology also optimizes the PA input and output return loss, giving a better matching than -20 dB at both input and output, and minimizing the risk of potential issues and performance degradation in the system integration phase. Lastly, the compact transformer based matching networks and quadrature hybrids reduce the chip area occupation of this PA, resulting in a compact design with competitive performance

Four-element phased-array beamformers and a self-interference canceling full-duplex transciver in 130-nm SiGe for 5G applications at 26 GHz

This thesis is on the design of radio-frequency (RF) integrated front-end circuits for next generation 5G communication systems. The demand for higher data rates and lower latency in 5G networks can only be met using several new technologies including, but not limited to, mm-waves, massive-MIMO, and full-duplex. Use of mm-waves provides more bandwidth that is necessary for high data rates at the cost of increased attenuation in air. Massive-MIMO arrays are required to compensate for this increased path loss by providing beam steering and array gain. Furthermore, full duplex operation is desirable for improved spectrum efficiency and reduced latency. The difficulty of full duplex operation is the self-interference (SI) between transmit (TX) and receive (RX) paths. Conventional methods to suppress this interference utilize either bulky circulators, isolators, couplers or two separate antennas. These methods are not suitable for fully-integrated full-duplex massive-MIMO arrays. This thesis presents circuit and system level solutions to the issues summarized above, in the form of SiGe integrated circuits for 5G applications at 26 GHz. First, a full-duplex RF front-end architecture is proposed that is scalable to massive-MIMO arrays. It is based on blind, RF self-interference cancellation that is applicable to single/shared antenna front-ends. A high resolution RF vector modulator is developed, which is the key building block that empowers the full-duplex frontend architecture by achieving better than state-of-the-art 10-b monotonic phase control. This vector modulator is combined with linear-in-dB variable gain amplifiers and attenuators to realize a precision self-interference cancellation circuitry. Further, adaptive control of this SI canceler is made possible by including an on-chip low-power IQ downconverter. It correlates copies of transmitted and received signals and provides baseband/dc outputs that can be used to adaptively control the SI canceler. The solution comes at the cost of minimal additional circuitry, yet significantly eases linearity requirements of critical receiver blocks at RF/IF such as mixers and ADCs. Second, to complement the proposed full-duplex front-end architecture and to provide a more complete solution, high-performance beamformer ICs with 5-/6- b phase and 3-/4-b amplitude control capabilities are designed. Single-channel, separate transmitter and receiver beamformers are implemented targeting massive- MIMO mode of operation, and their four-channel versions are developed for phasedarray communication systems. Better than state-of-the-art noise performance is obtained in the RX beamformer channel, with a full-channel noise figure of 3.3 d

High-Efficiency Millimeter-Wave Front-Ends for Large Phased-Array Transmitters

The ever-increasing demand for wireless broadband connectivity requires infrastructure capable of supporting data transfer rates at multi-Gbps. To accommodate such heavy traffic, the channel capacity for the given spectrum must be utilized as efficiently as possible. Wideband millimeter-wave phased-array systems can enhance the capacity of the channel by providing multiple steerable directional beams. However the cost, complexity, and high power consumption of phased-array systems are key barriers to the commercialization of such technology. Silicon-based beam-former chips and scalable phased-array technology offer promising solutions to lower the cost of phased-array systems. However, the implementation of low-power phased-array architectures is still a challenge. Millimeter-wave power generation in silicon beam-formers suffers from low efficiency. The stringent linearity requirements for multi-beam wideband arrays further limits the achievable efficiency. In scalable phased-arrays, each module consists of an antenna sub-array and a beam-former chip that feeds the antenna elements. To improve efficiency, a design methodology that considers the beam-former chip and the antenna array as one entity is necessary. In this thesis, power-efficient solutions for a millimeter-wave phased-array transmitter are studied and different high-efficiency power amplifier structures for broadband applications are proposed. Initially, the design of a novel 27-30 GHz RF front-end consisting of a variable gain amplifier, a 360 degree phase shifter, and a two-stage linear power amplifier with output power of 12 dBm is described. It is fabricated using 0.13 $\mu m$ SiGe technology. This chip serves as the RF core of a beam-former chip with eight outputs for feeding a 2$\times$2 dual-feed sub-array. Such sub-arrays are used as part of large phased-arrays for SATCOM infrastructure. Measurement results show 26.7 \% total efficiency for the designed chip. The chip achieves the highest efficiency among Ka-band phased-array transmitters reported in the literature. In addition, original transformer-based output matching structures are proposed for harmonic-tuned power amplifiers. Harmonic-tuned power amplifiers have high peak-efficiency but their complicated output matching structure can limit their use in beam-former RF front-ends. The proposed output matching structures have the layout footprint of a transformer, making their use in beam-former chips feasible. A 26-38 GHz power amplifier based on a non-inverting 1:1 transformer is fabricated. A measured efficiency of more than 27 \% is achieved across the band with an output power of 12 dBm. Furthermore, two continuous class $F^{-1}$ power amplifiers using 1:1 inverting transformers are described. Simulation results show a peak-efficiency of 35 \% and output power of 12 dBm from 24 to 30 GHz. A common-base power amplifier with inverting transformer output matching is also demonstrated. This amplifier achieves a peak-efficiency of 42 \% and peak output power of 16 dBm. Finally, a low-loss Ka-band re-configurable output matching structure based on tunable lines is proposed and implemented. A double-stub matching structure with three tunable segments is proposed to maximize the impedance matching coverage. This structure can potentially compensate for the antenna impedance variation in phased-array antennas

Low-Noise Amplifier and Noise/Distortion Shaping Beamformer

The emergence of advanced technologies has increased the need for fast and efficient mobile communication that can facilitate transferring large amounts of data and simultaneously serve multiple users. Future wireless systems will rely on millimeter-wave frequencies, enabled by recent silicon hardware advancements. High-frequency millimeter-wave technology and low-noise receiver front ends and amplifiers are key for improved performance and energy efficiency. This thesis proposes two LNA topologies that offer wide input-power-matched bandwidths and low noise figures, eliminating the need for complex matching networks at the LNA input. These topologies use intrinsic feedback through gate-drain networks and/or the resistance of the SOI-transistor back-gate terminal to achieve the real part of the input impedance. The two LNAs are experimentally demonstrated with two 22-nm FDSOI LNAs. One LNA, matched with the assistance of the gate-drain network, exhibits a bandwidth ranging from 7.7-33.3 GHz, which is further improved to 6-38.7 GHz through the application of the back-gate-resistance method. The two LNAs have noise-figure minima of 1.8 and 1.9 dB, maximum gains of 14.7 and 15.6 dB, and maximum IP1dBs of -9.1 and -7.8 dBm while consuming 10 and 7.8 mW of power and occupying 0.04 and 0.03 mm^2 of active areas, respectively. This thesis also presents the first experimental demonstration of noise/distortion (ND) shaping beamformer. The NDs originating in the receiver itself are spatio-temporally shaped away from the beamformer region of support, thereby permitting their suppression by the beamformer. The demonstrator is a 24.3-28.7 GHz, 79.28 mW 4-port receiver for a 4-element antenna array implemented in 22-nm FDSOI CMOS. When shaping was enabled, the concept demonstrator provided average improvements to the NF and IP1dB of 1.6 dB and 2.25 dB, respectively (compared to a reference design), and achieved NF=2.6 dB and IP1dB=-18.7dBm while consuming 19.8 mW/channel