Energy-efficient modulation and physical layer design for low terahertz band communication channel in 5G femtocell Internet of Things

© 2018 Elsevier B.V. High throughput capability of the terahertz band (0.3–10 THz) wireless communications is expected to be utilized by the fifth generation of mobile telecommunication systems and enable a plethora of new applications. Supporting devices will transfer large amounts of data in both directions, causing high energy consumption by the electronic circuitries of the equipment in use. Therefore, physical layer for these systems must be designed carefully in order to reduce energy consumption per bit. In this paper, the best performing modulation scheme and hardware parameters that minimize the energy consumption without affecting the system throughput are determined. THz band device technologies are outlined and a complete survey of the state-of-the-art low-THz band circuit blocks which are suitable for mass market production is given. It is shown that for short-range communications, M-ary quadrature amplitude modulation is the most energy-efficient technique that can lead up to 90% reduction in consumed energy. Moreover, optimal transceiver parameters which can be used to further minimize the energy consumption of the THz band system are examined

Terahertz Technology and Its Applications

The Terahertz frequency range (0.1 – 10)THz has demonstrated to provide many opportunities in prominent research fields such as high-speed communications, biomedicine, sensing, and imaging. This spectral range, lying between electronics and photonics, has been historically known as “terahertz gap” because of the lack of experimental as well as fabrication technologies. However, many efforts are now being carried out worldwide in order improve technology working at this frequency range. This book represents a mechanism to highlight some of the work being done within this range of the electromagnetic spectrum. The topics covered include non-destructive testing, teraherz imaging and sensing, among others

Overcome the Limitations of Performance Parameters of On-Chip Antennas Based on Metasurface and Coupled Feeding Approaches for Applications in System-on-Chip for THz Integrated-Circuits

YesThis paper proposes a new solution to improve the performance parameters of on-chip antenna designs on standard CMOS silicon (Si.) technology. The proposed method is based on applying the metasurface technique and exciting the radiating elements through coupled feed mechanism. The on-chip antenna is constructed from three layers comprising Si.-GND-Si. layers, so that the ground (GND) plane is sandwiched between two Si. layers. The silicon and ground-plane layers have thicknesses of 20μm and 5μm, respectively. The 3×3 array consisting of the asterisk-shaped radiating elements has implemented on the top silicon layer by applying the metasurface approach. Three slot lines in the ground-plane are modelled and located directly under the radiating elements. The radiating elements are excited through the slot-lines using an open-circuited microstrip-line constructed on the bottom silicon layer. The proposed method to excite the structure is based on the coupled feeding mechanism. In addition, by the proposed feeding method the on-chip antenna configuration suppresses the substrate losses and surface-waves. The antenna exhibits a large impedance bandwidth of 60GHz from 0.5THz to 0.56THz with an average radiation gain and efficiency of 4.58dBi and 25.37%, respectively. The proposed structure has compact dimensions of 200×200×45μm3. The results shows that, the proposed technique is therefore suitable for on-chip antennas for applications in system-on-chip for terahertz (THz) integrated circuits.Innovation programme under grant agreement H2020-MSCA-ITN-2016 SECRET-722424; UK Engineering and Physical Sciences Research Council (EPSRC) under grant EP/E0/22936/1.The full-text of this paper will be released for public view at the end of the publisher embargo on 11 Dec 2020

High performance on-chip array antenna based on metasurface feeding structure for terahertz integrated circuits

YesIn this letter a novel on-chip array antenna is investigated which is based on CMOS 20μm Silicon technology for operation over 0.6-0.65 THz. The proposed array structure is constructed on three layers composed of Silicon-Ground-Silicon layers. Two antennas are implemented on the top layer, where each antenna is constituted from three sub-antennas. The sub-antennas are constructed from interconnected dual-rings. Also, the sub-antennas are interconnected to each other. This approach enhances the aperture of the array. Surface waves and substrate losses in the structure are suppressed with metallic via-holes implemented between the radiation elements. To excite the structure, a novel feeding mechanism is used comprising open-circuited microstrip lines that couple electromagnetic energy from the bottom layer to the antennas on the top-layer through metasurface slot-lines in the middle ground-plane layer. The results show the proposed on-chip antenna array has an average radiation gain, efficiency, and isolation of 7.62 dBi, 32.67%, and -30 dB, respectively.H2020-MSCA-ITN-2016 SECRET-722424 and the financial support from the UK Engineering and Physical Sciences Research Council (EPSRC) under grant EP/E0/22936/

Study on On-Chip Antenna Design Based on Metamaterial-Inspired and Substrate Integrated Waveguide Properties for Millimetre-Wave and THz Integrated-Circuit Applications

This paper presents the results of a study on improving the performance parameters such as the impedance bandwidth, radiation gain and efficiency, as well as suppressing substrate loss of an innovative antenna for on-chip implementation for millimetre-wave and terahertz integrated-circuits. This was achieved by using the metamaterial and the substrate-integrated waveguide (SIW) technologies. The on-chip antenna structure comprises five alternating layers of metallization and silicon. An array of circular radiation patches with metamaterial-inspired crossed-shaped slots are etched on the top metallization layer below which is a silicon layer whose bottom surface is metalized to create a ground plane. Implemented in the silicon layer below is a cavity above which is no ground plane. Underneath this silicon layer is where an open-ended microstrip feedline is located which is used to excite the antenna. The feed mechanism is based on the coupling of the electromagnetic energy from the bottom silicon layer to the top circular patches through the cavity. To suppress surface waves and reduce substrate loss, the SIW concept is applied at the top silicon layer by implementing the metallic via holes at the periphery of the structure that connect the top layer to the ground plane. The proposed on-chip antenna has an average measured radiation gain and efficiency of 6.9 dBi and 53%, respectively, over its operational frequency range from 0.285–0.325 THz. The proposed on-chip antenna has dimensions of 1.35 × 1 × 0.06 mm3. The antenna is shown to be viable for applications in millimetre-waves and terahertz integrated-circuits

SILICON TERAHERTZ ELECTRONICS: CIRCUITS AND SYSTEMS FOR FUTURE APPLICATIONS

The terahertz frequency bands are gaining increasing attention these days for the potential applications in imaging, sensing, spectroscopy, and communication. These applications can be used in a wide range of fields, such as military, security, biomedical analysis, material science, astronomy, etc. Unfortunately, utilizing these frequency bands is very challenging due to the notorious ”terahertz gap”. Consequently, current terahertz systems are very bulky and expensive, sometimes even require cryogenic conditions. Silicon terahertz electronics now becomes very attractive, since it can achieve significantly lower cost and make portable consumer terahertz devices feasible. However, due to the limited device fmax and low breakdown voltage, signal generation and processing on silicon platform in this frequency range is challenging. This thesis aims to tackle these challenges and implement high-performance terahertz systems. First of all, the devices are investigated under the terahertz frequency range and optimum termination conditions for maximizing the efficacy of the devices is derived. Then, novel passive surrounding networks are designed to provide the devices with the optimal termination conditions to push the performances of the terahertz circuit blocks. Finally, the high-performance circuit blocks are used to build terahertz systems, and system-level innovations are also proposed to push the state of the art forward. In Chapter 2, using a device-centric bottom-up design method, a 210-GHz harmonic oscillator is designed. With the parasitic tuning mechanism, a wide frequency tuning range is achieved without using lossy varactors. A passive network based on the return-path gap coupler and self-feeding structure is also designed to provide optimal terminations for the active devices to maximize the harmonic power generation. Fabricated with a 0.13-um SiGe BiCMOS process, the oscillator is highly compact with a core size of only 290x95 um2. The output frequency can be tuned from 197.5 GHz to 219.7 GHz, which is around 10.6% compared to the center frequency. It also achieves a peak output power and dc-to-RF efficiency of 1.4 dBm and 2.4%, respectively. The measured output phase noise at 1 MHz offset is -87.5 dBc/Hz. The high power, wide tuning range, low phase noise, as well as compact size, make this oscillator very suitable for terahertz systems integration. In Chapter 3, the design of a 320-GHz fully-integrated terahertz imaging system is described. The system is composed of a phase-locked high-power transmitter and a coherent high-sensitivity subharmonic-mixing receiver, which are fabricated using a 0.13-um SiGe BiCMOS technology. To enhance the imaging sensitivity, a heterodyne coherent detection scheme is utilized. To obtain frequency coherency, fully-integrated phase-locked loops are implemented on both the transmitter and receiver chips. According to the measurement, consuming a total dc power of 605 mW, the transmitter chip achieves a peak radiated power of 2 mW and a peak EIRP of 21.1 dBm. The receiver chip achieves an equivalent incoherent responsivity of more than 7.26 MV/W and a sensitivity of 70.1 pW under an integration bandwidth of 1 kHz, with a total dc power consumption of 117 mW. The achieved sensitivity with this proposed coherent imaging transceiver is around ten times better compared with other state-of-the-art incoherent imagers. In Chapter 4, a spatial-orthogonal ASK transmitter architecture for high-speed terahertz wireless communication is presented. The self-sustaining oscillator-based transmitter architecture has an ultra-compact size and excellent power efficiency. With the proposed high-speed constant-load switch, significantly reduced modulation loss is achieved. Using polarization diversity and multi-level modulation, the throughput is largely enhanced. Array configuration is also adopted to enhance the link budget for higher signal quality and longer communication range. Fabricated in a 0.13-um SiGe BiCMOS technology, the 220-GHz transmitter prototype achieves an EIRP of 21 dBm and dc-to- THz-radiation efficiency of 0.7% in each spatial channel. A 24.4-Gb/s total data rate over a 10-cm communication range is demonstrated. With an external Teflon lens system, the demonstrated communication range is further extended to 52 cm. Compared with prior art, this prototype demonstrates much higher transmitter efficiency. In Chapter 5, an entirely-on-chip frequency-stabilization feedback mechanism is proposed, which avoids the use of both frequency dividers and off-chip references, achieving much lower system integration cost and power consumption. Using this mechanism, a 301.7-to-331.8-GHz source prototype is designed in a 0.13-um SiGe BiCMOS technology. According to the measurement, the source consumes a dc power of only 51.7 mW. The output phase noise is -71.1 and -75.2 dBc/Hz at 100 kHz and 1 MHz offset, respectively. A -13.9-dBm probed output power is also achieved. Overall, the prototype source demonstrates the largest output frequency range and lowest power consumption while achieving comparable phase noise and output power performances with respect to the state of the art. All the designs demonstrated in this thesis achieve good performances and push the state of the art forward, paving the way for implementation of more sophisticated terahertz circuits and systems for future applications

Packages for Terahertz Electronics

In the last couple of decades, solid-state device technologies, particularly electronic semiconductor devices, have been greatly advanced and investigated for possible adoption in various terahertz (THz) applications, such as imaging, security, and wireless communications. In tandem with these investigations, researchers have been exploring ways to package those THz electronic devices and integrated circuits for practical use. Packages are fundamentally expected to provide a physical housing for devices and integrated circuits (ICs) and reliable signal interconnections from the inside to the outside or vice versa. However, as frequency increases, we face several challenges associated with signal loss, dimensions, and fabrication. This paper provides a broad overview of recent progress in interconnections and packaging technologies dealing with these issues for THz electronics. In particular, emerging concepts based on commercial ceramic technologies, micromachining, and 3-D printing technologies for compact and lightweight packaging in practical applications are highlighted, along with metallic split blocks with rectangular waveguides, which are still considered the most valid and reliable approach.119Ysciescopu