High Tolerance of Charge Pump Leakage Current in Integer-N PLL Frequency Synthesizer for 5G Networks

One of the most promising solutions for the future fifth generation communication systems is to utilize millimeter wave (mm-W) radio frequencies. There is, however, little works about Phase Locked Loop (PLL) frequency synthesizer designed for mm-W band frequency for 5G applications. This article discusses integer PLL architecture for frequency synthesis; it targets the highest range of 5G mmW [81-86] GHz using ultra-wide channel spacing of 1GHz. This work investigates the design of a third passive loop filter for frequency synthesizer using a Phase Frequency Detector and a current switch Charge Pump such as analog devices ADF4155. The critical performance for the Charge Pump depends on the leakage current produced by the technology of its transistors. This undesirable current can have a high impact on the loop stability. However, by optimizing PLL filter parameters, the synthesizer was able to tolerate up to 117 nA. With such a high leakage current, a high performance of the system was achieved. As a result, less than −71 dBc reference spur level at 50 MHz offset frequency was ensured and 3.23 µs settling time for a hopping frequency of 5 GHz was achieved

Self-Calibrated, Low-Jitter and Low-Reference-Spur Injection-Locked Clock Multipliers

Department of Electrical EngineeringThis dissertation focuses primarily on the design of calibrators for the injection-locked clock multiplier (ILCM). ILCMs have advantage to achieve an excellent jitter performance at low cost, in terms of area and power consumption. The wide loop bandwidth (BW) of the injection technique could reject the noise of voltage-controlled oscillator (VCO), making it thus suitable for the rejection of poor noise of a ring-VCO and a high frequency LC-VCO. However, it is difficult to use without calibrators because of its sensitiveness in process-voltage-temperature (PVT) variations. In Chapter 2, conventional frequency calibrators are introduced and discussed. This dissertation introduces two types of calibrators for low-power high-frequency LC-VCO-based ILFMs in Chapter 3 and Chapter 4 and high-performance ring-VCO-based ILCM in Chapter 5. First, Chapter 3 presents a low power and compact area LC-tank-based frequency multiplier. In the proposed architecture, the input signals have a pulsed waveform that involves many high-order harmonics. Using an LC-tank that amplifies only the target harmonic component, while suppressing others, the output signal at the target frequency can be obtained. Since the core current flows for a very short duration, due to the pulsed input signals, the average power consumption can be dramatically reduced. Effective removal of spurious tones due to the damping of the signal is achieved using a limiting amplifier. In this work, a prototype frequency tripler using the proposed architecture was designed in a 65 nm CMOS process. The power consumption was 950 ??W, and the active area was 0.08 mm2. At a 3.12 GHz frequency, the phase noise degradation with respect to the theoretical bound was less than 0.5 dB. Second, Chapter 4 presents an ultra-low-phase-noise ILFM for millimeter wave (mm-wave) fifth-generation (5G) transceivers. Using an ultra-low-power frequency-tracking loop (FTL), the proposed ILFM is able to correct the frequency drifts of the quadrature voltage-controlled oscillator of the ILFM in a real-time fashion. Since the FTL is monitoring the averages of phase deviations rather than detecting or sampling the instantaneous values, it requires only 600??W to continue to calibrate the ILFM that generates an mm-wave signal with an output frequency from 27 to 30 GHz. The proposed ILFM was fabricated in a 65-nm CMOS process. The 10-MHz phase noise of the 29.25-GHz output signal was ???129.7 dBc/Hz, and its variations across temperatures and supply voltages were less than 2 dB. The integrated phase noise from 1 kHz to 100 MHz and the rms jitter were???39.1 dBc and 86 fs, respectively. Third, Chapter 5 presents a low-jitter, low-reference-spur ring voltage-controlled oscillator (ring VCO)-based ILCM. Since the proposed triple-point frequency/phase/slope calibrator (TP-FPSC) can accurately remove the three root causes of the frequency errors of ILCMs (i.e., frequency drift, phase offset, and slope modulation), the ILCM of this work is able to achieve a low-level reference spur. In addition, the calibrating loop for the frequency drift of the TP-FPSC offers an additional suppression to the in-band phase noise of the output signal. This capability of the TP-FPSC and the naturally wide bandwidth of the injection-locking mechanism allows the ILCM to achieve a very low RMS jitter. The ILCM was fabricated in a 65-nm CMOS technology. The measured reference spur and RMS jitter were ???72 dBc and 140 fs, respectively, both of which are the best among the state-of-the-art ILCMs. The active silicon area was 0.055 mm2, and the power consumption was 11.0 mW.clos

Design of 300 ghz combined doubler/subharmonic mixer based on schottky diodes with integrated mmic based local oscillator

In this paper the design and experimental characterization of a combined doublersubharmonic mixer based on Schottky diodes which uses a 75 GHz MMIC based local oscillator is presented. This solution integrates in the same substrate the doubler and the mixer, which share the same metallic packaging with the local oscillator. The prototype has been fabricated and measured. For characterization, the Y-Factor technique has been used and the prototype yields a best conversion loss and equivalent noise temperature of 11 dB and 1976 K, respectively, at 305 GHz. This performance is close to the state of the art, and shows the potential of this approach, which allows a significant reduction in terms of size and volume.This research was funded by the Spanish MINECO, Project No. TEC2016-76997-C3-1-R, and by the Spanish State Research Agency, Project No. PID2019-109984RB-C43/AEI/10.13039/501100011033

Algorithms and Circuits for Analog-Digital Hybrid Multibeam Arrays

Fifth generation (5G) and beyond wireless communication systems will rely heavily on larger antenna arrays combined with beamforming to mitigate the high free-space path-loss that prevails in millimeter-wave (mmW) and above frequencies. Sharp beams that can support wide bandwidths are desired both at the transmitter and the receiver to leverage the glut of bandwidth available at these frequency bands. Further, multiple simultaneous sharp beams are imperative for such systems to exploit mmW/sub-THz wireless channels using multiple reflected paths simultaneously. Therefore, multibeam antenna arrays that can support wider bandwidths are a key enabler for 5G and beyond systems. In general, N-beam systems using N-element antenna arrays will involve circuit complexities of the order of N2. This dissertation investigates new analog, digital and hybrid low complexity multibeam beamforming algorithms and circuits for reducing the associated high size, weight, and power (SWaP) complexities in larger multibeam arrays. The research efforts on the digital beamforming aspect propose the use of a new class of discrete Fourier transform (DFT) approximations for multibeam generation to eliminate the need for digital multipliers in the beamforming circuitry. For this, 8-, 16- and 32-beam multiplierless multibeam algorithms have been proposed for uniform linear array applications. A 2.4 GHz 16-element array receiver setup and a 5.8 GHz 32-element array receiver system which use field programmable gate arrays (FPGAs) as digital backend have been built for real-time experimental verification of the digital multiplierless algorithms. The multiplierless algorithms have been experimentally verified by digitally measuring beams. It has been shown that the measured beams from the multiplierless algorithms are in good agreement with the exact counterpart algorithms. Analog realizations of the proposed approximate DFT transforms have also been investigated leading to low-complex, high bandwidth circuits in CMOS. Further, a novel approach for reducing the circuit complexity of analog true-time delay (TTD) N-beam beamforming networks using N-element arrays has been proposed for wideband squint-free operation. A sparse factorization of the N-beam delay Vandermonde beamforming matrix is used to reduce the total amount of TTD elements that are needed for obtaining N number of beams in a wideband array. The method has been verified using measured responses of CMOS all-pass filters (APFs). The wideband squint-free multibeam algorithm is also used to propose a new low-complexity hybrid beamforming architecture targeting future 5G mmW systems. Apart from that, the dissertation also explores multibeam beamforming architectures for uniform circular arrays (UCAs). An algorithm having N log N circuit complexity for simultaneous generation of N-beams in an N-element UCA is explored and verified

Integrated Circuits and Systems for Millimeter-Wave Frequencies

In the first section of this thesis, mm-wave circuit- and system-level solutions for addition of multi-user service to conventional multi-antenna phased array architectures will be introduced. The proposed architecture will enhance the link capacity, co-channel user service and hardware cost compared to conventional solutions. Theory and design of the circuits and system are detailed and comprehensive measurement results are presented verifying the system-level functionality. First section is named A Millimeter-Wave Partially-Overlapped Beamforming-MIMO Receiver: Theory, Design, and Implementation. More specifically, this section presents an analysis and design of a partially-overlapped beamforming-MIMO architecture capable of achieving higher beamforming and spatial multiplexing gains with lower number of elements compared to conventional architectures. As a proof of concept, a 4-element beamforming-MIMO receiver (RX) covering 64-67 GHz frequency band enabling 2-stream concurrent reception is designed and measured. By partitioning the RX elements into two clusters and partially overlapping these clusters to create two 3-element beamformers, both phased-array (coherent beamforming) as well as MIMO (spatial multiplexing) features are simultaneously acquired. 6-bit phase shifters with 360° phase control and 5-bit VGAs with 11 dB range are designed to enable steering of the two RX clusters toward two arbitrary angular locations corresponding to two users. Fabricated in a 130-nm SiGe BiCMOS process, the RX achieves a 30.15 dB maximum direct conversion gain and a 9.8 dB minimum noise figure (NF) across 548 MHz IF bandwidth. S-parameter-based array factor measurements verify spatial filtering of the interference and spatial multiplexing in this RX chip.In the second section of this thesis, energy-efficient ultra-high speed transceiver architectures will be presented. Current high-speed transceivers rely on high-sampling-rate high-resolution power-hungry analog-to-digital converters or digital-to-analog converters at the interface of analog and digital circuitries. However, design of these backend data-converters are extremely power-hungry at very high speeds in a fully-integrated end-to-end scenario (i.e. RF-to-Bits, Bits-to-RF). Novel system-level architectures will be presented that obviate the need for such costly data converters and will significantly relax the complexity of digital signal-processing. The proposed architecture will result in orders of magnitude energy saving at ultra-high speeds. Theory, design, and measurement results of the highest-speed, highly energy-efficient fully-integrated end-to-end transceiver will be discussed in this section. Second section is named A Millimeter-Wave Energy-Efficient Direct-Demodulation Receiver: Theory, Design, and Implementation. More precisely, this section presents the theory, design, and implementation of an 8PSK direct-demodulation receiver based on a novel multi-phase RF-correlation concept. The output of this RF-to-bits receiver architecture is demodulated bits, obviating the need for power-hungry high-speed-resolution data converters. A single-channel 115-135-GHz receiver prototype was fabricated in a 55-nm SiGe BiCMOS process. A max conversion gain of 32 dB and a min noise figure (NF) of 10.3 dB was measured. A data-rate of 36 Gbps was wirelessly measured at 30 cm distance with the received 8PSK signal being directly demodulated on-chip at a bit-error-rate (BER) of 1e-6. The measured receiver sensitivity at this BER is -41.28 dBm. The prototype occupies 2.5 by 3.5 mm squared of die area including PADs and test circuits (2.5 mm squared active area) and consumes a total DC power of 200.25 mW

Integrated RF oscillators and LO signal generation circuits

This thesis deals with fully integrated LC oscillators and local oscillator (LO) signal generation circuits. In communication systems a good-quality LO signal for up- and down-conversion in transmitters is needed. The LO signal needs to span the required frequency range and have good frequency stability and low phase noise. Furthermore, most modern systems require accurate quadrature (IQ) LO signals. This thesis tackles these challenges by presenting a detailed study of LC oscillators, monolithic elements for good-quality LC resonators, and circuits for IQ-signal generation and for frequency conversion, as well as many experimental circuits. Monolithic coils and variable capacitors are essential, and this thesis deals with good structures of these devices and their proper modeling. As experimental test devices, over forty monolithic inductors and thirty varactors have been implemented, measured and modeled. Actively synthesized reactive elements were studied as replacements for these passive devices. At first glance these circuits show promising characteristics, but closer noise and nonlinearity analysis reveals that these circuits suffer from high noise levels and a small dynamic range. Nine circuit implementations with various actively synthesized variable capacitors were done. Quadrature signal generation can be performed with three different methods, and these are analyzed in the thesis. Frequency conversion circuits are used for alleviating coupling problems or to expand the number of frequency bands covered. The thesis includes an analysis of single-sideband mixing, frequency dividers, and frequency multipliers, which are used to perform the four basic arithmetical operations for the frequency tone. Two design cases are presented. The first one is a single-sideband mixing method for the generation of WiMedia UWB LO-signals, and the second one is a frequency conversion unit for a digital period synthesizer. The last part of the thesis presents five research projects. In the first one a temperature-compensated GaAs MESFET VCO was developed. The second one deals with circuit and device development for an experimental-level BiCMOS process. A cable-modem RF tuner IC using a SiGe process was developed in the third project, and a CMOS flip-chip VCO module in the fourth one. Finally, two frequency synthesizers for UWB radios are presented

Active Backscattering Positioning System Using Innovative Harmonic Oscillator Tags for Future Internet of Things: Theory and Experiments

RÉSUMÉ D'ici 2020, l'Internet des objets (IoT) permettra probablement de créer 25 milliards d'objets connectés, 44 ZB de données et de débloquer 11 000 milliards de dollars d’opportunités commerciales. Par conséquent, ce sujet a suscité d’énormes intérêts de recherche dans le monde académique entier. L'une des technologies clés pour l'IoT concerne le positionnement physique intérieur précis. Le principal objectif dans ce domaine est le développement d'un système de positionnement intérieur avec une grande précision, une haute résolution, un fonctionnement à plusieurs cibles, un faible coût, un faible encombrement et une faible consommation d'énergie. Le système de positionnement intérieur conventionnel basé sur les technologies de Wi-Fi ou d'identification par radiofréquence (RFID) ne peut répondre à ces exigences. Principalement parce que leur appareil et leur signal ne sont pas conçus spécialement pour atteindre les objectifs visés. Les chercheurs ont découvert qu'en mettant en oeuvre de différents types de modulation sur les étiquettes, le radar à onde continue (CW) et ses dérivés deviennent des solutions prometteuses. Les activités de recherche présentées dans cette thèse sont menées dans le but de développer des systèmes de positionnement en intérieur bidimensionnel (2-D) à plusieurs cibles basées sur des étiquettes actives à rétrodiffusion harmonique avec une technique à onde continue modulée en fréquence (FMCW). Les contributions de cette thèse peuvent être résumées comme suit: Tout d'abord, la conception d'un circuit actif harmonique, plus spécifiquement une classe d'oscillateurs harmoniques innovants utilisée comme composant central des étiquettes actives dans notre système, implique une méthodologie de conception de signal de grande taille et des installations de caractérisation. L’analyseur de réseau à grand signal (LSNA) est un instrument émergent basé sur les fondements théoriques du cadre de distorsion polyharmonique (PHD). Bien qu'ils soient disponibles dans le commerce depuis 2008, des organismes de normalisation et de recherche tels que l’Institut national des normes et de la technologie (NIST) des États-Unis travaillent toujours à la mise au point d'un standard largement reconnu permettant d'évaluer et de comparer leurs performances. Dans ce travail, un artefact de génération multi-harmonique pour la vérification LSNA est développé. C'est un dispositif actif capable de générer les 5 premières harmoniques d'un signal d'entrée avec une réponse ultra-stables en amplitude et en phase, quelle que soit la variation de l'impédance de la charge.----------ABSTRACT By 2020, the internet of things (IoT) will probably enable 25 billion connected objects, create 44 ZB data and unlock 11 trillion US dollar business opportunities. Therefore, this topic has been attracting tremendous research interests in the entire academic world. One of the key enabling technologies for IoT is concerned with accurate indoor physical positioning. The development of such an indoor positioning system with high accuracy, high resolution, multitarget operation, low cost, small footprint, and low power consumption is the major objective in this area. The conventional indoor positioning system based on WiFi or radiofrequency identification (RFID) technology cannot fulfill these requirements mainly because their device and signal are not purposely designed for achieving the targeted goals. Researchers have found that by implementing different types of modulation on the tags, continuous-wave (CW) radar and its derivatives become promising solutions. The research activities presented in this Ph.D. thesis are carried out towards the goal of developing multitarget two-dimensional (2-D) indoor positioning systems based on harmonic backscattering active tags together with a frequency-modulated continuous-wave (FMCW) technique. Research contributions of this thesis can be summarized as follows: First of all, the design of a harmonic active circuit, more specifically, a class of innovative harmonic oscillators used as the core component of active tags in our system, involves a large signal design methodology and characterization facilities. The large signal network analyzer (LSNA) is an emerging instrument based on the theoretical foundation for the Poly-Harmonic Distortion (PHD) framework. Although they have been commercially available since 2008, standard and research organizations such as the National Institute of Standards and Technology (NIST) of the US are still working towards a widely-recognized standard to evaluate and cross-reference their performances. In this work, a multi-harmonic generation artifact for LSNA verification is developed. It is an active device that can generate the first 5 harmonics of an input signal with ultra-stable amplitude and phase response regardless of the load impedance variation