77 research outputs found

    A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

    Get PDF
    © 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.A fully-integrated reconfigurable dual-band (760-960 MHz and 2.4-2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PA's operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by x3.24 and x1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by x2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.Peer reviewe

    Design and implementation of frequency synthesizers for 3-10 ghz mulitband ofdm uwb communication

    Get PDF
    The allocation of frequency spectrum by the FCC for Ultra Wideband (UWB) communications in the 3.1-10.6 GHz has paved the path for very high data rate Gb/s wireless communications. Frequency synthesis in these communication systems involves great challenges such as high frequency and wideband operation in addition to stringent requirements on frequency hopping time and coexistence with other wireless standards. This research proposes frequency generation schemes for such radio systems and their integrated implementations in silicon based technologies. Special emphasis is placed on efficient frequency planning and other system level considerations for building compact and practical systems for carrier frequency generation in an integrated UWB radio. This work proposes a frequency band plan for multiband OFDM based UWB radios in the 3.1-10.6 GHz range. Based on this frequency plan, two 11-band frequency synthesizers are designed, implemented and tested making them one of the first frequency synthesizers for UWB covering 78% of the licensed spectrum. The circuits are implemented in 0.25µm SiGe BiCMOS and the architectures are based on a single VCO at a fixed frequency followed by an array of dividers, multiplexers and single sideband (SSB) mixers to generate the 11 required bands in quadrature with fast hopping in much less than 9.5 ns. One of the synthesizers is integrated and tested as part of a 3-10 GHz packaged receiver. It draws 80 mA current from a 2.5 V supply and occupies an area of 2.25 mm2. Finally, an architecture for a UWB synthesizer is proposed that is based on a single multiband quadrature VCO, a programmable integer divider with 50% duty cycle and a single sideband mixer. A frequency band plan is proposed that greatly relaxes the tuning range requirement of the multiband VCO and leads to a very digitally intensive architecture for wideband frequency synthesis suitable for implementation in deep submicron CMOS processes. A design in 130nm CMOS occupies less than 1 mm2 while consuming 90 mW. This architecture provides an efficient solution in terms of area and power consumption with very low complexity

    Clock Generation Design for Continuous-Time Sigma-Delta Analog-To-Digital Converter in Communication Systems

    Get PDF
    Software defined radio, a highly digitized wireless receiver, has drawn huge attention in modern communication system because it can not only benefit from the advanced technologies but also exploit large digital calibration of digital signal processing (DSP) to optimize the performance of receivers. Continuous-time (CT) bandpass sigma-delta (ΣΔ) modulator, used as an RF-to-digital converter, has been regarded as a potential solution for software defined ratio. The demand to support multiple standards motivates the development of a broadband CT bandpass ΣΔ which can cover the most commercial spectrum of 1GHz to 4GHz in a modern communication system. Clock generation, a major building block in radio frequency (RF) integrated circuits (ICs), usually uses a phase-locked loop (PLL) to provide the required clock frequency to modulate/demodulate the informative signals. This work explores the design of clock generation in RF ICs. First, a 2-16 GHz frequency synthesizer is proposed to provide the sampling clocks for a programmable continuous-time bandpass sigma-delta (ΣΔ) modulator in a software radio receiver system. In the frequency synthesizer, a single-sideband mixer combines feed-forward and regenerative mixing techniques to achieve the wide frequency range. Furthermore, to optimize the excess loop delay in the wideband system, a phase-tunable clock distribution network and a clock-controlled quantizer are proposed. Also, the false locking of regenerative mixing is solved by controlling the self-oscillation frequency of the CML divider. The proposed frequency synthesizer performs excellent jitter performance and efficient power consumption. Phase noise and quadrature phase accuracy are the common tradeoff in a quadrature voltage-controlled oscillator. A larger coupling ratio is preferred to obtain good phase accuracy but suffer phase noise performance. To address these fundamental trade-offs, a phasor-based analysis is used to explain bi-modal oscillation and compute the quadrature phase errors given by inevitable mismatches of components. Also, the ISF is used to estimate the noise contribution of each major noise source. A CSD QVCO is first proposed to eliminate the undesired bi-modal oscillation and enhance the quadrature phase accuracy. The second work presents a DCC QVCO. The sophisticated dynamic current-clipping coupling network reduces injecting noise into LC tank at most vulnerable timings (zero crossing points). Hence, it allows the use of strong coupling ratio to minimize the quadrature phase sensitivity to mismatches without degrading the phase noise performance. The proposed DCC QVCO is implemented in a 130-nm CMOS technology. The measured phase noise is -121 dBc/Hz at 1MHz offset from a 5GHz carrier. The QVCO consumes 4.2mW with a 1-V power supply, resulting in an outstanding Figure of Merit (FoM) of 189 dBc/Hz. Frequency divider is one of the most power hungry building blocks in a PLL-based frequency synthesizer. The complementary injection-locked frequency divider is proposed to be a low-power solution. With the complimentary injection schemes, the dividers can realize both even and odd division modulus, performing a more than 100% locking range to overcome the PVT variation. The proposed dividers feature excellent phase noise. They can be used for multiple-phase generation, programmable phase-switching frequency dividers, and phase-skewing circuits

    Design and implementation of frequency synthesizers for 3-10 ghz mulitband ofdm uwb communication

    Get PDF
    The allocation of frequency spectrum by the FCC for Ultra Wideband (UWB) communications in the 3.1-10.6 GHz has paved the path for very high data rate Gb/s wireless communications. Frequency synthesis in these communication systems involves great challenges such as high frequency and wideband operation in addition to stringent requirements on frequency hopping time and coexistence with other wireless standards. This research proposes frequency generation schemes for such radio systems and their integrated implementations in silicon based technologies. Special emphasis is placed on efficient frequency planning and other system level considerations for building compact and practical systems for carrier frequency generation in an integrated UWB radio. This work proposes a frequency band plan for multiband OFDM based UWB radios in the 3.1-10.6 GHz range. Based on this frequency plan, two 11-band frequency synthesizers are designed, implemented and tested making them one of the first frequency synthesizers for UWB covering 78% of the licensed spectrum. The circuits are implemented in 0.25µm SiGe BiCMOS and the architectures are based on a single VCO at a fixed frequency followed by an array of dividers, multiplexers and single sideband (SSB) mixers to generate the 11 required bands in quadrature with fast hopping in much less than 9.5 ns. One of the synthesizers is integrated and tested as part of a 3-10 GHz packaged receiver. It draws 80 mA current from a 2.5 V supply and occupies an area of 2.25 mm2. Finally, an architecture for a UWB synthesizer is proposed that is based on a single multiband quadrature VCO, a programmable integer divider with 50% duty cycle and a single sideband mixer. A frequency band plan is proposed that greatly relaxes the tuning range requirement of the multiband VCO and leads to a very digitally intensive architecture for wideband frequency synthesis suitable for implementation in deep submicron CMOS processes. A design in 130nm CMOS occupies less than 1 mm2 while consuming 90 mW. This architecture provides an efficient solution in terms of area and power consumption with very low complexity

    Design of Low-Power Short-Distance Transceiver for Wireless Sensor Networks

    Get PDF
    Ph.DDOCTOR OF PHILOSOPH

    Radiowave propagation and antennas for high data rate mobile communications in the 60 GHz band

    Get PDF
    The 60 GHz MIMO systems are seen as some of the best candidates for the implementation of future high data-rate short range communications systems such as wireless personal area networks (WPAN). Although the performance of MIMO systems has been studied thoroughly theoretically and experimentally at lower frequencies like at 2 and 5 GHz, there is a clear lack of measurement data and experimental performance evaluations of MIMO techniques at 60 GHz. Furthermore, more effort is still needed in the design and evaluation of compact low cost 60 GHz antennas for communication applications. In the first part of the thesis, the first 60 GHz MIMO channel measurement system is presented. It is based on a previously developed 2 and 5 GHz sounder and frequency converters. This system uses virtual antenna arrays to create the channel matrix. A measurement campaign is reported. In order to improve the delay resolution, two other MIMO measurement systems are presented, based on an ultra wide band (UWB) sounder and a vector network analyzer (VNA). Those systems allow full characterization of the MIMO channel in the delay and angular domains. In the second part of this work, the performance of multi-antenna techniques is evaluated based on the measurement data obtained in the first part of the thesis. Three of the most promising multi-antenna techniques, namely MIMO, antenna selection MIMO, and beam steering, are analyzed and compared. The presented results indicate that the mutual information of the measured MIMO channel is quite close to that of the independent and identically distributed (i.i.d.) MIMO Rayleigh channel. Furthermore, in realistic conditions it is seen that MIMO-antenna selection often leads to lower mutual information than traditional MIMO with the same number of RF chains. Moreover, it is shown that when considering phase shifters with realistic losses, MIMO technique almost always outperforms beam steering technique. In the last part of the thesis a 60 GHz planar omnidirectional antenna is presented. This antenna is very suitable for communications applications since it has low profile and uses a metal layer only on one side of the substrate. Therefore, it can be manufactured easily and at very low cost. In addition, an advanced quasi full 3-D radiation pattern measurement system has been developed to evaluate probe-fed antennas. Very good measurement repeatability is reported. The radiation of the probe is analyzed and is seen to be the main limitation of the dynamic range of the measurement setup
    corecore